Let me confirm about a function of "Keeper” which is described in reference manual.
I'm confused about that.
There are two words which are very similar.
One is "Internal Keeper”, the other is "Pad keeper”.
Is it same meaning ?
There are following description in 9.1 Pin Control and GPIO Overview.
"All EMI pins' internal keepers can be disabled to allow them to change to a highimpedance
state (as required by some DRAM manufacturers).”
How can I judge whether DRAM manufactures require a high impedance state or not ?
IMX28 digital pins have internal keepers, which are configured,
using PINCTRL Pad Keeper Disable Registers.
Use DRAM specs, provided in Datasheets, regarging high impedance
I have not found the mentioned requirements about high impedance in
Datasheets for the following DRAM devices, that can be used with i.MX28:
MT46H64M16 and EDE1116AEBG.
Hi Yuri Muhin
I found a description which is written as required specification in P10 of following document .
I think it's a requirements about high impedance.
Am I correct ?
Furthermore, do you have any document for internal circuit when user set internal keeper to disable ?
I can't figure out what kind of difference will occur internally when I disable it.
the mentioned specs (from Samsumg) are standard requirements for DRAM signals during
operations, when data bus state should be dynamically changed. The i.MX28 keeper option
are used to configure pin's state for relatively long time (statically). As general example, it makes
sense for multi-master system, when one master should free bus for others.
Hope the following tutorial helps to understand keeper operation.