Footnote 4 of eSDHC Input Hold Time (SD8) of i.MX6D

[takayuki_ishii]

Hello community.

I have one question about footnote4 of SD/MMC Interface Timing Specification.

Table 50. SD/eMMC4.3 Interface Timing Specification in datasheet IMX6DQAEC Rev. 6, 11/2018 

It have footnote 4 as following,

4. To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

Is it meaning that each hold time between SD_CLK <-> SD_CMD, SD_CLK <-> SD_D1, SD_CLK <-> SD_D2 ... SD_CLK <-> SD_D7 must not exceed 2 ns ?

Please see attached document "SDR104_HoldTiming_2ns.xlsx".

Best regards,

Ishii.

[nxf63675 · Accepted solution]

Hi @takayuki_ishii,

Your understanding is correct, the time between data must not exceed 2nS.

Regards,

Israel.