I am designing a Custom based on IMX6Q/D/Dual Lite and using four DDR3 and planning to use Fly-by topology for routing.
HW Design Checking List for i.Mx6 Rev2.5 has Ref-a5 that has recommendation for DDR3 routing by group. Does these guidelines apply to tree topology routing only? If yes are there Fly-by topology guidelines as well.
Please let me know as I am setting up the routing constraints and will be very helpful.
you can use the same recommendations (described in HW Design Checking List)
for Fly-by topology guidelines as well. However since these recommendations are difficult
to implement, it is highly recommended to use ibis modelling.
Freescale has not reference design with Fly-by topology, so there are no
recommendations in HW Design Checking List.
I have seen an aplpication note AN3940 from Freescale. It is not necessarily for IMX6 processors but since DDR3 design is standard, can I use the recommendation from there. This seems to be more logical and implementable than that givein in i.Mx6 Rev2.5 checklist for a fly by topology.
I am of the view that i.Mx6 Rev2.5 recommendations are more suited to Tree-topology and also works well when DDR3 chips are mounted on both sides of the board.
Please let me know if you think otherwise.