FEC DRIVER STALLED ISSUE IN IMX6SL

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FEC DRIVER STALLED ISSUE IN IMX6SL

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himabindu
Contributor III

Hi Team,

    

               Currently I am working on IMX6 Sololite Linux Kernel Version-3.10.17. I tried with the Latest Kernel version-4.1.2.

I am facing the ethernet speed and stalled issues while transmitting or receiving the files using scp.

                Kindly help me in resolving the stalled issue and speed issue while transferring the Files using Ethernet. I am using pll6_enet as the Reference clock(50 MHz) and clock is defined with a period of 26 MHz speed.

 

time scp uImage 192.168.1.13:/root/
root@192.168.2.13's password:
uImage 63% 3488KB 0.0KB/s - stalled

kernel Debug Messages for FEC Driver:

=================================

[    1.289558] Reference Clock:[50000000]
[    1.297676] MII GASKET Register- For RMII Mode
[    1.302155] 1.CFGR Value:1
[    1.305003] Speed:[20]
[    1.311335] libphy: fec_enet_mii_bus: probed

[   17.744541] fec 2188000.ethernet eth0: Freescale FEC PHY driver [Micrel KSZ8081 or KSZ8091] (mii_bus:phy_addr=2188000.ethernet:00, irq=-1)
[   17.774792] IPv6: ADDRCONF(NETDEV_UP): eth0: link is ready

The following are my dts and dtsi files. Can I know which is making the file Transmission or Reception slower :-

arch/arm/mach-imx/mach-imx6sl.c :-

=============================

static void __init imx6sl_fec_clk_init(void)
{
        struct regmap *gpr;

           gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sl-iomuxc-gpr");
        if (!IS_ERR(gpr)) {
                regmap_update_bits(gpr, IOMUXC_GPR1,
                        IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK, 1); //To indicate clock is supplied externally to the processor.
                regmap_update_bits(gpr, IOMUXC_GPR1,
                        IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK, 0);
        } else
                pr_err("failed to find fsl,imx6sl-iomux-gpr regmap\n");
}

fec assignment in imx6sl-evk.dtsi :-

==========================

&fec {
pinctrl-names = "sleep";
pinctrl-0 = <&pinctrl_fec_1>;
pinctrl-1 = <&pinctrl_fec_1_sleep>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio4 21 0>;
phy-reset-duration = <1>;
status = "okay";
};

Interrupts and Clocks in imx6sl.dtsi:

=====================

fec: ethernet@02188000 {
compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
reg = <0x02188000 0x4000>;
interrupts = <0 114 0x04>;
clocks = <&clks IMX6SL_CLK_ENET>,
<&clks IMX6SL_CLK_ENET_REF>;
clock-names ="enet","pll6_enet";
status = "disabled";
};

Pins in imx6sl.dtsi :

=====================

 fec {
                pinctrl_fec_1: fecgrp-1 {
                        fsl,pins = <
                                MX6SL_PAD_FEC_TX_CLK__FEC_TX_CLK   0x1b0b0      
                                MX6SL_PAD_FEC_MDC__FEC_MDC         0x1b0b0
                                MX6SL_PAD_FEC_MDIO__FEC_MDIO       0x1b0b0
                                MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV    0x1b0b0
                                MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0   0x1b0b0
                                MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1   0x1b0b0
                                MX6SL_PAD_FEC_TX_EN__FEC_TX_EN     0x1b0b0
                                MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0   0x1b0b0
                                MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1   0x1b0b0
                                MX6SL_PAD_FEC_RX_ER__FEC_RX_ER     0x1b0b0      
                                MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
                        >;
                };

                pinctrl_fec_1_sleep: fecgrp-1-sleep {
                        fsl,pins = <
                                MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21  0x80000000
                                MX6SL_PAD_FEC_MDC__GPIO4_IO23      0x80000000
                                MX6SL_PAD_FEC_MDIO__GPIO4_IO20     0x80000000
                                MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25   0x80000000
                                MX6SL_PAD_FEC_RXD0__GPIO4_IO17     0x80000000
                                MX6SL_PAD_FEC_RXD1__GPIO4_IO18     0x80000000
                                MX6SL_PAD_FEC_TX_EN__GPIO4_IO22    0x80000000
                                MX6SL_PAD_FEC_TXD0__GPIO4_IO24     0x80000000
                                MX6SL_PAD_FEC_TXD1__GPIO4_IO16     0x80000000
                                MX6SL_PAD_FEC_RX_ER__GPIO4_IO19    0x80000000   
                                MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26  0x4001b0a8
                        >;
                };
        };

Thanks & Regards,

C.Himabindu.

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diegoadrian
NXP Employee
NXP Employee

Hello

C.Himabindu,

Thank you for writing.

Can you please check if your output frequency, is the same as the one you are specifying in the device tree?

Best regards,

Diego.

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himabindu
Contributor III

Hai Diego,

            Thankyou for your answer. Actually we dont specify any frequency in dts file.

The clock frequency of 50 Mhz is passing externally to the processor. Also 50 Mhz is consistent throughout the file transfer using scp.

But the Transfer is getting stalled in between.

Thanks & Regards,

C.Himabindu.

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himabindu
Contributor III

Hai Diego,

               Finally I am able to resolve the Ethernet Stalled Issue and Speed issue while transferring the Files using SCP.

The following Changes have been made to indicate that clock is externally supplied to the Processor.

CHANGE-1:-

============

imx6sl_fec_clk_init without modifications:-

 =================================

  regmap_update_bits(gpr, IOMUXC_GPR1,IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK, 0);
  regmap_update_bits(gpr, IOMUXC_GPR1,IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK, 0);

#define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17)
#define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14)

imx6sl_fec_clk_init with modifications:-

==================================

  regmap_update_bits(gpr, IOMUXC_GPR1,14, 1);
  regmap_update_bits(gpr, IOMUXC_GPR1,17, 0);

CHANGE-2:-

==========

phy-reset is not required.So fec_of_init and phy_reset parts of code are not required.

static void fec_of_init(struct platform_device *pdev)
{
        struct device_node *np = pdev->dev.of_node;
        struct net_device *ndev = platform_get_drvdata(pdev);
        struct fec_enet_private *fep = netdev_priv(ndev);
        int err;

        /*
         * init phy-reset-gpio to one invalid GPIO for no phy
         * gpio reset platform
         */
        fep->phy_reset_gpio = -1;

        if (!np)
                return;

        of_property_read_u32(np, "phy-reset-duration",
                                 &fep->reset_duration);
        /* A sane reset duration should not be longer than 1s */
        if ((fep->reset_duration > 1000) || (fep->reset_duration == 0))
                fep->reset_duration = 1;

        fep->phy_reset_gpio = of_get_named_gpio(np, "phy-reset-gpios", 0);
        if (!gpio_is_valid(fep->phy_reset_gpio))
                return;

        err = devm_gpio_request_one(&pdev->dev, fep->phy_reset_gpio,
                                    GPIOF_OUT_INIT_HIGH, "phy-reset");
        if (err) {
                dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
                fep->phy_reset_gpio = -1;
        }
}


static void fec_reset_phy(struct platform_device *pdev)
{
        struct net_device *ndev = platform_get_drvdata(pdev);
        struct fec_enet_private *fep = netdev_priv(ndev);

        /* check GPIO valid to avoid kernel print warning when no gpio reset */
        if (gpio_is_valid(fep->phy_reset_gpio)) {
                gpio_set_value(fep->phy_reset_gpio, 0);
                msleep(fep->reset_duration);
                gpio_set_value(fep->phy_reset_gpio, 1);
        }
}

cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
                                ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;

The following gasket configuration bit(cfgr) as 1 will indicate that RMII Mode is Enabled.

CHANGE-3:

===========

 clock-names = "enet", "pll6_enet";

Changed the Reference Clock to pll6_enet as this will provide a clock frequency of 50 Mhz instead of

ipg clock which will provide clock frequency of 66MHz to Processor.

Thanks & Regards,

C.Himabindu.

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diegoadrian
NXP Employee
NXP Employee

I am glad that you solved your problem.

Also, thank you for share your workaround.

Best Regards,

Diego.

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