External Trigger for IPU on i.MX6

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External Trigger for IPU on i.MX6

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uwehalmich
Contributor I

Hi,

we are designing a camera for a client. The client has a second camera and likes to syncronize the VSYNC of both. We are now trying to synchronize the display interface (DI) of the IPU with an external trigger from our clients system.

The datasheet has some hints for doing something like this, but nothing clear. There is a ext_vsync signal in the block diagram of the DI, but I can't find it anywhere else in the datasheet.

It seems like there is a possibility to sync with the CSI-modules but that hasn't worked yet. I think it lacks of the correct settings of CSI.

We also tried to manipulate the counters in the DI0_Sync_Wave_Gen registers, but that is more like guessing. Everyone of these counters have a external sync option, but it's not clear from where these external syncs may come. Is there probably a possibility to trigger these counters from the ARM, so we can synchronize with a GPIO Interrupt?

Has anyone tried something similar or have any hints where to start? Any help would be greatly appreciated.

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david_babin
NXP Employee
NXP Employee

In the IOMUX Controller chapter of the reference manual, I found both CSI0_VSYNC associated with IPU1 and CSI1_VSYNC associated with IPU2. CSI0_VSYNC has it's own ball which is called CSI0_VSYNC. However, CSI1_VSYNC is muxed through both EIM_DATA29 (Alt6) and EIM_AD12 (Alt2). For proper mux control, ensure that the SION bit = 0.

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uwehalmich
Contributor I

Hello David,

thank you very much for your reply.

I set the IOMUX with the mxc_iomux_v3_setup_pad() function with MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC as argument. I also tried various settings in the CSI-module itself (including the test mode), but it won't work. I ensured that the pin is routed through on the board with GPIO.

Maybe I don't understand the DI0_SYNC_WAVE_GEN0/1 in it's entirety and thats the problem. I set the counter for the VSYNC to di0_cnt_auto_reload=0 and the di0_cnt_clr_sel_2 to CSI_VSYNC. The signal connected to CSI0_VSYNC is a 25Hz pulse. The other counter-registers are set with fbset to 1024x768@25Hz.

IPU_CONF: 00000660

IPU_PM: 08100810

IPU_GPR: 00000000

DISP_GEN: 01600000

DI_GENERAL: 00300000

DI_BASE_SYNC_CLOCK_GEN 0: 00000010

DI_BASE_SYNC_CLOCK_GEN 1: 00010000

DI0_SW_GEN0_1: 2d010000

DI0_SW_GEN0_2: 2d010001

DI0_SW_GEN0_3: 1a1a0000

DI0_SW_GEN0_4: 0003004b

DI0_SW_GEN0_5: 00010509

DI0_SW_GEN1_1: 10000000

DI0_SW_GEN1_2: 30e01000

DI0_SW_GEN1_3: 20bc2000

DI0_SW_GEN1_4: 08000000

DI0_SW_GEN1_5: 0a000000

DI0_SYNC_AS_GEN: 00004002


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