External Interrupt support in i.MX537

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External Interrupt support in i.MX537

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prateekraghuvan
Contributor II

Hi All,

          Please tell me if there is any external interrupt support in i.MX537, reference manual suggested that some GPIO has the such capability but

I didn't get any  documentation on it. Please suggest any workaround if any.

Thanks

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RodBorras
NXP Employee
NXP Employee

Hi Prateek,

Yes, the MX53 has the ability to interrupt from many GPIO inputs:

a) GPIO1 (32 pins) through GPIO4 (32 pins) can be configured to generate interrupts when the pins are set to inputs

b) GPIO2 through GPIO4 do not have an "ARM interrupt" for each pin, but rather for the OR'ed results of 16 pins

     ==> e.g. GPIO2 will cause an "ARM IRQ 52" if there is a valid interrupt on any pin within 0-15

     ==> e.g. GPIO2 will cause an "ARM IRQ 53" if there is a valid interrupt on any pin within 16-31

     ==> So even though GPIO2 can monitor 32 pins for activity, the ARM Core will only see 1 of 2 IRQs happen (#52 or #53)

c) GPIO1 has the same functionality as described in b), but also some further granularity: its bottom 8 pins (0-7) will cause 8 specific "ARM interrupts"

     ==> GPIO1_0 will cause an "ARM IRQ 49", and so on for pins 1,2,3,4,5,6; GPIO1_7 will cause an "ARM IRQ 42"

     ==> for GPIO1_8 through GPIO1_31, these can only be seen through "ARM IRQ98" for pins 0-15, or "ARM IRQ99" for pins 16-31

d) In addition, all the 8 registers for the specific GPIOx need to be configured correctly:

   - GPIOx_IMR: the appropriate bits need to be set to 1 to enable those interrupts

   - GPIOx_ISR: the interrupt routine must write a 1 to the appropriate bit to clear the interrupt flag

   - GPIOx_ICR1 and GPIOx_ICR2: these allow you to select between level (low or high) or edge (rising or falling) for the given interrupt pin

   - GPIOx_EDGE_SEL: this allows you to override GPIOx_ICR1 and GPIOx_ICR2 for historical reasons

   - GPIOx_GDIR: the appropriate pin must be set to an input (bit=0) to allow for interrupts

   - GPIOx_DR and GPIO_PSR: not relevant here

e) Finally, you need to use the IOMUX Controller to set the specific pins to be in GPIO mode


Regards,

Rod.

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prateekraghuvan
Contributor II

Hi RodBorras,

                    Thank you for your answer. It is really helpful. Is it also described in the datasheet or reference manual of the processor? if yes, then Please point me to it.

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RodBorras
NXP Employee
NXP Employee

Hi Prateek,

RM=Reference Manual

- the IRQ numbers and breakout can be found in RM Table 3-1, page 215

- the GPIO registers can be found in RM chapter 37

- the OR'ed function of the GPIO interrupts is explained in RM pages 1723, 1724, 1726

Regards,

Rod.

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mujeebshaik
Contributor II

Hi Rod,

I am using i.MX53 QSB Board,i want to acces the GPIOs from Application,as i obsereved there is no access to GPIO from user space(Application layer),the GPIO functions are DDK level, i want to access them from application please suggest me the way to access the GPIO from Application.

Thnaks & Regards,

Shaik.

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