Exception on LDREX to 0x80000000~0xdfffffff on Cortex-M4 of i.MX6 SoloX

[guohuxu]

Hi Freescale Experts,

I want to place the data region of the customized OS in DDR RAM under the PS bus access, but LDREX to these locations leads to exception.

If I use LDREX to access the DDR RAM by PC bus, everything works fine. Running the code on DDR RAM by PC bus is OK.

There is also no problem to use LDREX to access the OCRAM by PS bus(0x20900000).

My questions are: Do I miss any setting for LDREX access to DDR by PS bus? Or is there any constrain for LDREX access to DDR by PS bus?

Thanks,

Best Regards,

Guohu

[igorpadykov]

Hi Guohu

Resource Domain Controller (RDC) allows isolation between cores,

so one can try to configure it properly, check Chapter 52 IMX6SXRM.

Best regards

igor

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[guohuxu]

Hi Igor,

Thank you for replying!

But I think the default settings of RDC is enough for Cortex M4 to access DDR RAM via PS bus.

The justifications are as following:

1. The default Domain ID of Cortex M4 is 0, which is same as Cortex A9. The Peripheral Domain Access Permissions allow all Resource Domains to access All peripheral. The Memory Regions are disabled, so they should be bypassed.

2. LDR/STR instructions is OK to DDR RAM via PS bus. But LDREX leads exception. I don't see any additional constrain description for LDREX by contrasting to normal memory access LDR/STR.

I also found that  the PS cache cannot be enabled. The LMEM_PSCCR(0xe0002800) register is always 0 whatever value is written. Does that matter?

Best Regards,

Guohu

[karina_valencia]

igorpadykov​ can you   continue with  the follow up?

[igorpadykov]

Hi Guohu

>I also found that  the PS cache cannot be enabled. The LMEM_PSCCR(0xe0002800) register is

>always 0 whatever value is written. Does that matter?

yes it may be the reason. Actually all accesses to ddr from m4 are done using

caches, please look at sect.13.9.3.1 Processor Code accesses,

sect.13.9.3.2 Processor Space accesses i.MX6SX Reference Manual (rev.0  2/2015)

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SXRM.pdf

You said that used customized OS, since processors that have ldrex/strex

are new enough and have a big bank of config registers accessed through coprocessor reads,

could you try with NXP software (uboot/linux)

Board Support Packages (32)

L3.14.28_1.0.0_iMX6SX_BUNDLE (REV L3.14.28_1.0.0)

http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/i.mx-applications-process...

Best regards

igor

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Note: If this post answers your question, please click the Correct Answer button. Thank you!

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[guohuxu]

Hi Igor,

I've been told that the Cortex-M4 core didn't support LDREX/STREX since there is no global lock monitor on CM4.

So I'll avoid using LDREX/STREX instructions on CM4.

Thanks!

Best Regards,

Guohu