We are trying to configure the KSZ8081RNB ethernet chip over management signals MDC and MDIO.
Clock quality is similar to evaluation board, however when CPU is trying to read the address, each time PHY chip is returning different address. This is not happening in Evaluation board. Clock frequency 2.35MHz.
Can anyone help us on this issue.
Here I want to add pne more thing that EVK board has used external 1.8V to drive reference power pin of PHY.
However we have not used external one.
Will it make any impact.
I feel the external pin is for powering up of the chip, if so, the device tree will have the entry of the pin doing so.
In your present case, have you taken care of the pin settings in Device tree?
It will be more helpful, if you could attach both the device tree files here.
However datasheet mantions that this reference pin must not be powered. Still EVK has connected it.
What do you mean by by device tree?
Do you see some other issue by which we are not getting proper data on MDIO pin.+