Hello,
I am using a custom board derived from the Sabre Smart Device from Freescale. I managed to adapt the 2014 version of u-boot to start the board. The system start correctly, but there is a problem with our PHY (which is of course different than the sabre SDB one).
Here is the output of u-boot :
U-Boot 2014.10-rc2 (Oct 01 2014 - 10:24:31)
CPU: Freescale i.MX6SOLO rev1.1 at 792 MHz
Reset cause: WDOG
Board: MX6S-Vendome
I2C: ready
DRAM: 512 MiB
MMC: FSL_SDHC: 0
No panel detected: default to Hannstar-XGA
Display: Hannstar-XGA (1024x768)
In: serial
Out: serial
Err: serial
PMIC: PFUZE100 ID=0x10
Net: Phy not found
PHY reset timed out
FEC [PRIME]
Hit any key to stop autoboot: 0
=> ping 192.1.1.48
Using FEC device
ARP Retry count exceeded; starting again
ARP Retry count exceeded; starting again
ARP Retry count exceeded; starting again
ARP Retry count exceeded; starting again
ARP Retry count exceeded; starting again
Abort
ping failed; host 192.1.1.48 is not alive
=> mii info
PHY 0x00: OUI = 0x5043, Model = 0x22, Rev = 0x02, 100baseT, FDX
=> mii dump 0 0
0. (3100) -- PHY control register --
(8000:0000) 0.15 = 0 reset
(4000:0000) 0.14 = 0 loopback
(2040:2000) 0. 6,13 = b01 speed selection = 100 Mbps
(1000:1000) 0.12 = 1 A/N enable
(0800:0000) 0.11 = 0 power-down
(0400:0000) 0.10 = 0 isolate
(0200:0000) 0. 9 = 0 restart A/N
(0100:0100) 0. 8 = 1 duplex = full
(0080:0000) 0. 7 = 0 collision test enable
(003f:0000) 0. 5- 0 = 0 (reserved)
In u-boot 2009, the code of the PHY is very close to the sabre SDB one. Only the "mx6_rgmii_rework" need to be modified. here is the old code:
int mx6_rgmii_rework(char *devname, int phy_addr)
{
unsigned short val;
#if 0
/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
phy_write(devname, phy_addr, 0xd, 0x7);
phy_write(devname, phy_addr, 0xe, 0x8016);
phy_write(devname, phy_addr, 0xd, 0x4007);
phy_read(devname, phy_addr, 0xe, &val);
val &= 0xffe3;
val |= 0x18;
phy_write(devname, phy_addr, 0xe, val);
/* introduce tx clock delay */
phy_write(devname, phy_addr, 0x1d, 0x5);
phy_read(devname, phy_addr, 0x1e, &val);
val |= 0x0100;
phy_write(devname, phy_addr, 0x1e, val);
#endif
}
// FJ disable crossover cable detection
phy_read(devname, phy_addr, 0x10, &val);
val &= 0xFFCF;
phy_write(devname, phy_addr, 0x10, val);
return 0;
}
I do not know what to look for to resolve this problem...
Thank you in advance for your help !