Ethernet PHY configuration

[seetha]

Hello all,

I am working on i.MX53 WinCE 7.0. Now my PHY read and write is not happening properly. Could you please help me to add a new PHY configuration in the source code. I am confused where exactly I need to put the new PHY configuration and my MIIREAD() function is returning FALSE. It is not properly reading the PHY registers. I have following questions.

1) Where I need to update the new PHY configuration?

2) Why MIIREAD() function is not properly happening?

3) I have the PHY ID but if I read the PHY ID, it is displaying some junk values. What may be the issue?

4)Could you please send me the example settings file that I need to do in order add my PHY settings?

Please help in solving the issues.

Thank you,

Seetharam

[mnw]

The standard code should work OK for you to get the PHY ID, UNLESS you are using different signals for MDC and MDIO to the ones used on the other Freescale designs.  Another option would be to diff your modified Linux code vs the Freescale code - that should give you some clues as to what to change. 

[seetha]

Thanks for the reply. Now MDC and MDIO lines setup in the sense only IOMUX setup ? Or I need to see MDC clock or something. According datasheet they explain about the MDC as follows.

Internal MAC clock frequency     MSCR [MII_SPEED]                            MDC frequency
25 MHz                                      0x4                                                         2.50 MHz
33 MHz                                      0x6                                                        2.36 MHz
40 MHz                                     0x7                                                        2.50 MHz
50 MHz                                      0x9                                                        2.50 MHz
66 MHz                                      0xD                                                       2.36 MHz

This is actually MSCR register of Ethernet hardware.Based on Internal MAC clock frequency I need to write the MII_SPEED part of MSCR register and  then it will set MDC frequency accordingly.

What is the generic setup of MDC and MDIO in Ethernet? For the PHY to get detected and read/write to happen only MDC and MDIO IOMUX settings enough ? Do I need to set any clock as they shown in the datasheet.?

Thanks for your support,

Seetharam

[mnw]

Good question.  You should only need to setup the MDC and MDIO lines. The standard code should be fine unless you are using different pins for these signals.

[seetha]

We are using crystal(ABM8G-25.000MHZ-18)  not an oscillator says my hardware team. How many clock's need to be set for PHY to get detected. Now I am mainly concentrating on PHY detection, MIIREAD() , MIIWRITE() and I am working on eboot for that to happen . So how many things(changes) that I need to check to make the PHY detected in eboot level and for read/write to PHY happen? Can you please share it with me? 

Thanks for your support,

Seetharam

[mnw]

It's hard to say without seeing your schematics.  Does your oscillator have an enable pin?

[seetha]

Since in Linux OS Ethernet is working properly, according to Hardware the clock is properly driven. And after probing the PHY pins small difference in TX Clock and MDC found between WinCE and Linux. Is there anything else that I am missing to be set through software? Do I need to set clock through software? How can I do that? Please suggest..

Thanks,

Seetharam

[mnw]

This is a hardware thing.  The clock signals on the PHY and MX53 are inputs so you should be driving them with an oscillator.

[seetha]

Hi Martin, 

Could you please help me in setting the clock for PHY and Clock for FEC controller? In my case as of now, MIIREAD() is returning 0 and I do not think MIIWRITE() will happen. So how do I set the PHY clock?

Thanks,

Seetharam

[mnw]

I would focus on getting the ID before worrying about too much else for now.  I see your PHY has MII interface, so you will have a bit of work to do getting the extra lines setup in the mux.  Also double check your MDC and MDIO signals are setup to the correct pins.

The phys.h stuff is used for CE.  Once you have the OAL code working, you may need to change the Config or Startup sections in phys.h to match.  My changes will not help you here!

[seetha]

Hello Martin, 

Thanks a lot for your reply. Could you please share the changes that you have done in your files that you mentioned. I have done the most of the changes that you have told in your reply. I will cross check that with my files. I seriously doubt on my PHY settings that I have done phys.h. We are using KSZ9021 PHY from Micrel. 

Please share the files.

Thank you

Seetharam

Martin Welford said:

Hi Setharam

We have a different PHY on our design and changed the following files to get it working in eboot and CE:

platform\Common\src\soc\COMMON_FSL_V3\FEC\chip.c

platform\Common\src\soc\COMMON_FSL_V3\FEC\fec.h

platform\Common\src\soc\COMMON_FSL_V3\FEC\phys.h

platform\Common\src\soc\COMMON_FSL_V3\OAL\COMMON\ETHDRV\FEC\fec.c

platform\Common\src\soc\COMMON_FSL_V3\OAL\COMMON\ETHDRV\FEC\fec.h

Our changes involve copying an existing phy, renaming and modifying to match the correct settings.

If you are not getting the ID correctly, you will need to check your hardware for things like:

 - correct pullups on the MDIO line (QSB has 1k)

 - correct clocking for the PHY and FEC_REF_CLK

Best regards

Martin

[mnw]

Hi Setharam

We have a different PHY on our design and changed the following files to get it working in eboot and CE:

platform\Common\src\soc\COMMON_FSL_V3\FEC\chip.c

platform\Common\src\soc\COMMON_FSL_V3\FEC\fec.h

platform\Common\src\soc\COMMON_FSL_V3\FEC\phys.h

platform\Common\src\soc\COMMON_FSL_V3\OAL\COMMON\ETHDRV\FEC\fec.c

platform\Common\src\soc\COMMON_FSL_V3\OAL\COMMON\ETHDRV\FEC\fec.h

Our changes involve copying an existing phy, renaming and modifying to match the correct settings.

If you are not getting the ID correctly, you will need to check your hardware for things like:

 - correct pullups on the MDIO line (QSB has 1k)

 - correct clocking for the PHY and FEC_REF_CLK

Best regards

Martin