Hi,
We designed a custom i.MX6ULL board, which takes most of the schematic from the EVAL board.
Our application only requires one ethernet connection, so one PHY was omitted. Unfortunately, a small mistake was made in the design; the PHY address strapping from ENET 1 was used for ENET2.
Subsequently, the PHY is not recognised.
However, I see no part of the devicetree that specifies the PHY address:
fec1: ethernet@2188000 {
compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
reg = <0x02188000 0x4000>;
interrupt-names = "int0", "pps";
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_ENET>,
<&clks IMX6UL_CLK_ENET_AHB>,
<&clks IMX6UL_CLK_ENET_PTP>,
<&clks IMX6UL_CLK_ENET_REF>,
<&clks IMX6UL_CLK_ENET_REF>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
fsl,num-tx-queues=<1>;
fsl,num-rx-queues=<1>;
status = "disabled";
};
any advise is appreciated !
