We got i.MX 8DXL A1 System from NXP in munich
It attached Micron (16-bit, LP42400, 1GB). I replaced it samsung memory "K4F4E164HD-THCL"
it's a 16-bt, LP4 2400, 0.5GB
So, I changed some parameters in RPA files.
| Device Information | | |
| SoC: | iMX8DXL |
| Memory type: | LPDDR4 |
| Manufacturer: | Micron |
| Memory part number: | MT53D512M16D1 |
| Density per channel per chip select (Gb)1: | 4 |
| Number of Channels (based on Bus Width)3 | 1 |
| Number of Chip Selects used2 | 1 |
| Total DRAM density (Gb) | 4 |
| Number of bits for ROW address2 | 16 |
| Number of bits for COLUMN address2 | 10 |
| Number of bits for BANK address2 | 3 |
| Number of BANKS2 | 8 |
| Bus Width | 16 |
| Clock Cycle Freq (MHz) | 1200 |
| Clock Cycle Time (ns) | 0.833333333 |
| DDRC0 Base Address (do not modify) | 5C000000 |
| PHY0 Base Address (do not modify) | 5C010000 |
after run stress test, It shows fail as below,
DDR configuration | DDR type is LPDDR4 | Data width: 16, bank num: 8 | Row size: 16, col size: 10 | One chip select is used | Number of DDR controllers used on the SoC: 1 | Density per chip select: 1024MB | Density per controller is: 1024MB | Total density detected on the board is: 1024MB | | | Command Bus Training was executed | No DDR data training errors detected for DDRC0 | ============================================ | | | MX8QXP: Cortex-A35 is found | | | ************************************************************************* | DDR Stress Test Iteration 1 | -------------------------------- | --Running DDR test on region 1-- | -------------------------------- | | | t0.1: data is addr test | ...Address of failure: 0x00000000A0000000 | Data read was: 0x0000000084000000 | But pattern was: 0x0000000080000000 |
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Also I tried to change row address from 16 to 15, 14 It that case shows as below as below
VREF training error detected | Write DQS2DQ training error detected |
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