Enabling UART1 and UART4 using device tree

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Enabling UART1 and UART4 using device tree

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dhanyahc
Contributor II

Hi

I am using iMX6 dual core processor from Phytec (phyBOARD-Mira i.MX6). In that by default UART2 and UART3 are configured. similarly I modified device tree files to enable UART1 and UART4. But I still see only two UART(tty) ports listed under /dev. Could someone help me to figure out where I am going wrong.

// Added PIN control for UART1 and UART4 (UARt2 was already present)

pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_EIM_D26__UART2_TX_DATA0x1b0b1
MX6QDL_PAD_EIM_D27__UART2_RX_DATA0x1b0b1
>;
};

pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA0x1b0b1
MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA0x1b0b1
>;
};

pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA0x1b0b1
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA0x1b0b1
>;
};

// Added node for UART1 and UART4

&uart1 {

  pinctrl-names = "default";

  pinctrl-0 = <&pinctrl_uart1>;

  status = "disabled";

};

&uart2 {

  pinctrl-names = "default";

  pinctrl-0 = <&pinctrl_uart2>;

  status = "disabled";

};

&uart4 {

  pinctrl-names = "default";

  pinctrl-0 = <&pinctrl_uart4>;

  status = "disabled";

};

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dhanyahc
Contributor II

Finally found exact root cause of the problem.

UART1 and UART4 RX and TX Pins were reversed.

and also we need replace status = "disabled" with status = "okay" (didn't work initially as RX and TX pins were reserved)

Status of UART2 and UART3 was was over written in .dts file hence those two UARTs were enabled even though status was set to disabled in .dtsi

View solution in original post

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emptyfridge
Contributor II

Hi Guys,

I try to enable UART5 with device tree overlay. The UART is enabled and showed up in the /dev/ttymxc4 and in the boot log:

[ 3.719766] 21f4000.serial: ttymxc4 at MMIO 0x21f4000 (irq = 302, base_baud = 5000000) is a IMX

But I can not measure any TX mgs.

device tree overlay:

/dts-v1/;
/plugin/;

#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6q-pinfunc.h"

/ {
fragment@0{
   target = <&pinctrl_uart5>;
   __overlay__ {
            fsl,pins = <
                  MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 /* M4 CSI0_DAT14 UART5_TX_DATA */
                  MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 /* M5 CSI0_DAT15 UART5_RX_DATA */
                  MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1 /* L6 CSI0_DAT19 UART5_CTS_B */
                  MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1 /* M6 CSI0_DAT18 UART5_RTS_B */
                  MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x80000000 /* C22 RGMII_TD0 GPIO6_IO20  */
                  MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x80000000 /* F20 RGMII_TD1 GPIO6_IO21  */
                  MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x80000000 /* E21 RGMII_TD2 GPIO6_IO22  */
           >;
      };
};

fragment@1{
      target = <&uart5>;
         __overlay__ {
            status = "okay";
            pinctrl-names = "default";
            pinctrl-0 = <&pinctrl_uart5>;
         };
      };
};

in base devtree:

&iomuxc {

uart5 {
/* empty group for device tree overlay */
   pinctrl_uart5: uart5grp {
   };
};

};

_________________________________________________________________________________________

If I do the configuration in the "normal" device tree. Everything works fine and I can measure the TX out msgs.

[ 1.115512] 21f4000.serial: ttymxc4 at MMIO 0x21f4000 (irq = 70, base_baud = 5000000) is a IMX

normal Device tree:

&iomuxc {

uart5 {
/* empty group for device tree overlay */
   pinctrl_uart5: uart5grp {
      fsl,pins = <
            MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 /* M4 CSI0_DAT14 UART5_TX_DATA */
            MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 /* M5 CSI0_DAT15 UART5_RX_DATA */
            MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1 /* L6 CSI0_DAT19 UART5_CTS_B */
            MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1 /* M6 CSI0_DAT18 UART5_RTS_B */
            MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x80000000 /* C22 RGMII_TD0 GPIO6_IO20 */   
            MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x80000000 /* F20 RGMII_TD1 GPIO6_IO21 */   
            MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x80000000 /* E21 RGMII_TD2 GPIO6_IO22 */
      >;
   };
};

};

&uart5 {
   status = "okay";
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_uart5>;
};

I do not see any reason, why this should not work with devtree overlay... 

kernel version

Linux 4.9.123-10 #1 SMP Thu Oct 31 22:12:41 UTC 2019 armv7l armv7l armv7l GNU/Linux

Board:

:~# cat /proc/cpuinfo
processor : 0
model name : ARMv7 Processor rev 10 (v7l)
BogoMIPS : 3.00
Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpd32
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x2
CPU part : 0xc09
CPU revision : 10

processor : 1
model name : ARMv7 Processor rev 10 (v7l)
BogoMIPS : 3.00
Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpd32
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x2
CPU part : 0xc09
CPU revision : 10

Hardware : Freescale i.MX6 Quad/DualLite (Device Tree)
Revision : 0000
Serial : 0000000000000000

Thanks for your Help

regards

tom

OK, I think I got it. Unfortunately it looks like it is not possible to do the pin muxing in a overlay fragment...

at least with my used kernel version....

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dhanyahc
Contributor II

Finally found exact root cause of the problem.

UART1 and UART4 RX and TX Pins were reversed.

and also we need replace status = "disabled" with status = "okay" (didn't work initially as RX and TX pins were reserved)

Status of UART2 and UART3 was was over written in .dts file hence those two UARTs were enabled even though status was set to disabled in .dtsi

View solution in original post

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kkd1
Contributor III

Hi,

I am also working on "how to enable uart 2,3,&4 in imx6 Iwg15 Pico solo/q/d/l boards"

1) I made status of all uart port "okay" in arch/ arm/boot/dtsi file.

2) So 4 uart are enable,but no communication happened!

i.e.

echo "test string" >/dev/ttymxc2 ======> no write operation.

3)in boot log it shows:

... 

Serial: IMX driver
2020000.serial: ttymxc0 at MMIO 0x2020000 (irq = 58, base_baud = 5000000) is a IMX
21e8000.serial: ttymxc1 at MMIO 0x21e8000 (irq = 59, base_baud = 5000000) is a IMX
console [ttymxc1] enabled
21ec000.serial: ttymxc2 at MMIO 0x21ec000 (irq = 60, base_baud = 5000000) is a IMX
imx6dl-pinctrl 20e0000.iomuxc: pin MX6DL_PAD_KEY_COL0 already requested by 20e0000.iomuxc; cannot claim for 21f0000.serial
imx6dl-pinctrl 20e0000.iomuxc: pin-145 (21f0000.serial) status -22
imx6dl-pinctrl 20e0000.iomuxc: could not request pin 145 (MX6DL_PAD_KEY_COL0) from group uart4-q7-pico on device 20e0000.iomuxc
imx-uart 21f0000.serial: Error applying setting, reverse things back
21f0000.serial: ttymxc3 at MMIO 0x21f0000 (irq = 61, base_baud = 5000000) is a IMX
serial: Freescale lpuart driver
imx sema4 driver is registered.

.....

 

 that means conflicting of two pins with another peripheral/module pin.

I tried to comment another utilisation,but still no success!!!

Also by checking on DSO there is no pulses at pin EIM_D25 pins.

Is any further changes requires ? 

Please guide

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dhanyahc
Contributor II

Thanks Igor.  I will use this file as reference to modify/ configure other peripheral.

I am not understanding why UART2 and UART3 were listed under device list even though status = "disabled"

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dhanyahc
Contributor II

Thanks Saurabh for your quick replay. Your suggestion works.

Now I see all configured UARTs are listed under device list (but I am test to test  functionality).

But I am not understanding why UART2 and UART3 were listed under device list even though status = "disabled".

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igorpadykov
NXP TechSupport
NXP TechSupport

one can look at riot board for example:

linux-2.6-imx.git - Freescale i.MX Linux Tree

~igor

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saurabh206
Senior Contributor III

Hi

You need to replace status = "disabled" with   status = "ok" to enable device.

Thanks

Saurabh

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davidvescovi
Contributor IV

wrong. needs to be "okay"

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