Enable sai2 & sai3 interfaces in imx8qxp

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Enable sai2 & sai3 interfaces in imx8qxp

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Contributor I

Hi all,

         We are using i.MX 8QuadXPlus with audio codecs, so need to use sai2 & sai3 interfaces for audio routing to codecs

         Taking an imx-xtor.c driver for creating driver for sai2 & sai3.

         Please help us to resolve issue

Facing issues :

 fsl-sai 59060000.sai: ASoC: can't open platform 59060000.sai: -6
 fsl-sai 59060000.sai: ASoC: can't open platform 59060000.sai: -6
 fsl-sai 59070000.sai: ASoC: can't open platform 59070000.sai: -6
 fsl-sai 59070000.sai: ASoC: can't open platform 59070000.sai: -6

Configured sai2 & sai3 interfaces in device tree file

fsl-imx8qxp-mek.dtsi:

+    sound-bt {
+        compatible = "fsl,imx-audio-xtor-bt";
+        model = "xtor-bt-audio";
+        cpu-dai = <&sai2>;
+        status = "okay";
+    };
+
+    sound-hfa {
+        compatible = "fsl,imx-audio-xtor-hfa";
+        model = "xtor-hfa-audio";
+        cpu-dai = <&sai0>;
+        status = "okay";
+    };
+    sound-fm {
+        compatible = "fsl,imx-audio-xtor-fm";
+        model = "xtor-fm-audio";
+        cpu-dai = <&sai3>;
         status = "okay";
     };
 
@@ -184,7 +204,7 @@
         compatible = "fsl,imx-audio-xtor";
         model = "xtor-audio";
         cpu-dai = <&sai0>;
-        status = "okay";
+        status = "disabled";
     };
 
     lvds_backlight0: lvds_backlight@0 {
@@ -538,6 +558,23 @@
             >;
         };
 
+        pinctrl_sai2: sai2grp {
+            fsl,pins = <
+                SC_P_CSI_D03_ADMA_SAI2_RXC    0x06000040
+                SC_P_CSI_D04_ADMA_SAI2_RXD    0x06000040
+                SC_P_CSI_D05_ADMA_SAI2_RXFS 0x06000040
+            >;
+        };
+
+        pinctrl_sai3: sai3grp {
+            fsl,pins = <
+                SC_P_CSI_D06_ADMA_SAI3_RXC    0x06000040
+                SC_P_CSI_D07_ADMA_SAI3_RXD    0x06000040
+                SC_P_CSI_HSYNC_ADMA_SAI3_RXFS 0x06000040
+            >;
+        };
+
+
         pinctrl_usdhc1: usdhc1grp {
             fsl,pins = <
                 SC_P_EMMC0_CLK_CONN_EMMC0_CLK        0x06000041
@@ -950,6 +987,26 @@
     pinctrl-0 = <&pinctrl_sai1>;
     status = "okay";
 };
+&sai2 {
+    assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>,
+            <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>,
+            <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>,
+            <&clk IMX8QXP_AUD_SAI_2_MCLK>;
+    assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_sai2>;
+    status = "okay";
+};
+&sai3 {
+    assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>,
+            <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>,
+            <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>,
+            <&clk IMX8QXP_AUD_SAI_3_MCLK>;
+    assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_sai3>;
+    status = "okay";
+};
 

Added edma channels in the below file:

fsl-imx8dx.dtsi:

<0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */
<0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */
+ <0x0 0x59300000 0x0 0x10000>, /* sai2 rx */
+ <0x0 0x59310000 0x0 0x10000>, /* sai3 rx */
<0x0 0x59350000 0x0 0x10000>,
<0x0 0x59370000 0x0 0x10000>;
#dma-cells = <3>;
shared-interrupt;
- dma-channels = <16>;
+ dma-channels = <18>;
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
@@ -2813,6 +2815,8 @@
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, /* sai2 */
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* sai3 */
<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* asrc0 */
@@ -2822,6 +2826,8 @@
"edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */
"edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */
"edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */
+ "edma0-chan16-rx", /* sai2 */
+ "edma0-chan17-rx", /* sai3 */
"edma0-chan21-tx", /* gpt5 */
"edma0-chan23-rx"; /* gpt7 */
status = "okay";

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47 Views
NXP TechSupport
NXP TechSupport

Hi Santhana

regarding "Added edma channels", probably old kernel used in the case, suggest

to try latest like  L4.14.98_GA kernel where dmas property were properly defined

fsl-imx8dx.dtsi\freescale\dts\boot\arm64\arch - linux-imx - i.MX Linux kernel 

Best regards
igor
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