Ehternet doesn't work in uboot

[MicMoba]

Hi,

I have an issue with my ethernet in uboot. U-Boot 2018.03. In Linux the ethernet works well so I can assume that the hardware is okay.

MyHardware:

i.MX6Q

PHY: Microchip LAN8720A

Phy is connected by RMII as described in Hardware Development Guide for i.MX6 Chapter 12.

Ethernet-Phy (LAN8720)	Prozessor (i.MX6)
MDIO (12)	ENET_MDIO (V23)
MDC (13)	ENET_MDC (V20)
RXD0 (8)	ENET_RXD0 (W21)
RXD1 (7)	ENET_RXD1 (W22)
CRS_DV (11)	ENET_CRS_DV (U21)
TXD0 (17)	ENET_TXD0 (U20)
TXD1 (18)	ENET_TXD1 (W20)
TXEN (16)	ENET_TX_EN (V21)
RST (15)	EIM_BCLK (N22)
XTAL1/CLKIN (5)	GPIO16 (R2)
RXER (10)	ENET_RX_ER (W23)
INT (14)	n.c.

I configure GPIO16 as clock output (50MHz). I can measure the 50MHz at pin 5 of LAN8720. During the initialisatzion first I configure ENET_RXD0, ENET_RXD1, ENET_CRS_DV and ENET_RX_ER as GPIO and set them all to high to set the mode and address of the PHY. Then I assert a PHY reset and deassert it after 10ms. Then I reconfigure ENET_RXD0, ENET_RXD1, ENET_CRS_DV and ENET_RX_ER.

In uboot I can communicate with the PHY over MII or MDIO. I checked the signals with a logic analyser and it looks okay.

=> mdio list
FEC:
1 - SMSC LAN8710/LAN8720 <--> FEC

=> mii info 1
fec_mdio_read: phy: 01 reg:03 val:0xc0f1
fec_mdio_read: phy: 01 reg:02 val:0x7
fec_mdio_read: phy: 01 reg:00 val:0x3100
fec_mdio_read: phy: 01 reg:05 val:0xcde1
fec_mdio_read: phy: 01 reg:04 val:0x1e1
fec_mdio_read: phy: 01 reg:00 val:0x3100
fec_mdio_read: phy: 01 reg:05 val:0xcde1
fec_mdio_read: phy: 01 reg:04 val:0x1e1
PHY 0x01: OUI = 0x01F0, Model = 0x0F, Rev = 0x01, 100baseT, FDX

But when I want to do a ping-command I always got the following message:

=> ping 192.168.0.155Using FEC device
ARP Retry count exceeded; starting again
ping failed; host 192.168.0.155 is not alive

=> pri ipaddr
ipaddr=192.168.0.75

After some investigation I add a few debug outputs to the fec_mxc.c to check the pin muxing.

=> ping 192.168.0.155
eth_halt: wait for stop regs
eth_halt: done
fec_mii_setspeed: mii_speed 0000001a
fec_open: fec_open(dev)
[fec_open] fec->eth->ecntrl: 0x2188024, reg: 0xf0000102
[fec_open]: use PHYLIB
fec_mdio_read: phy: 01 reg:01 val:0x782d
fec_mdio_read: phy: 01 reg:01 val:0x782d
fec_mdio_read: phy: 01 reg:01 val:0x782d
fec_mdio_read: phy: 01 reg:04 val:0x1e1
fec_mdio_read: phy: 01 reg:05 val:0xcde1
[fec_open]: speed = 100
fec_open:Speed=100
[fec_open]: ENET_RDAR 0x1000000
Using FEC device
IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO           (0x20E01D0): 0x00000001
IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER          (0x20E01D8): 0x00000001
IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV         (0x20E01DC): 0x00000001
IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1       (0x20E01E0): 0x00000001
IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0       (0x20E01E4): 0x00000001
IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN          (0x20E01E8): 0x00000001
IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1       (0x20E01EC): 0x00000001
IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0       (0x20E01F0): 0x00000001
IOMUXC_SW_MUX_CTL_PAD_ENET_MDC            (0x20E01F4): 0x00000001
IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK            (0x20E0158): 0x00000005
IOMUXC_SW_MUX_CTL_PAD_GPIO16              (0x20E0248): 0x00000012
IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO           (0x20E04E4): 0x0001b0b0
IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER          (0x20E04EC): 0x0001b0b0
IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV         (0x20E04F0): 0x0001b0b0
IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1       (0x20E04F4): 0x0001b0b0
IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0       (0x20E04F8): 0x0001b0b0
IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN          (0x20E04FC): 0x0001b0b0
IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1       (0x20E0500): 0x0001b0b0
IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0       (0x20E0504): 0x0001b0b0
IOMUXC_SW_PAD_CTL_PAD_ENET_MDC            (0x20E0508): 0x0001b0b0
IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK            (0x20E046C): 0x000000f1
IOMUXC_SW_PAD_CTL_PAD_GPIO16              (0x20E0618): 0x000000e1
IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT        (0x20E0840): 0x00000000
IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT      (0x20E0844): 0x00000000
IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT    (0x20E0848): 0x00000001
IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT    (0x20E084C): 0x00000001
IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT       (0x20E0858): 0x00000001
IOMUXC_ENET_REF_CLK_SELECT_INPUT          (0x20E083C): 0x00000001
CCM_ANALOG_PLL_ENET                       (0x20C80E0): 0x80102001
IOMUXC_GPR1                               (0x20E0004): 0x48602005
[fec_open]: ENET_TDAR 0x01000000
[fec_send]: timeout TDAR
fec_send: status 0x8c00 index 0 ret -22
fec_recv: ievent 0x0
fec_recv: status 0x8000
fec_recv: stop
fec_recv: ievent 0x0
fec_recv: status 0x8000
fec_recv: stop
fec_recv: ievent 0x0
fec_recv: status 0x8000
...

I checked the signals on RXD0, RXD1, TXD0 and TXD1 at the PHY while I enter the ping-command. I can see nothing. No edges, nothing. All lines are low.

So is there a missconfiguration of my pin muxing? Is there a clock missing? Currently I am quite at a loss and I lack ideas.

Thanks.

Regards Michael

[MicMoba]

Hi,

I found the issue. The PHY is connected over RMII and the following config was the mistake:

#define CONFIG_FEC_XCV_TYPE RGMII

It has to be

#define CONFIG_FEC_XCV_TYPE RMII

:smileyconfused: