ERR050310: CM7 Icache/Dcache are not operational on i.MX8 Nano SoC

[jpsk]

Hi,

Based on the errata sheet and Ref Manual 4.2.2.2, we must NOT enable the caches on the CM7 core.  If the code size is below 256K, run from TCM.  My questions are:

1. How do I make sure the caches are disabled in CM7 core?

2. Since my code size is bigger than 256K and I have to run the code from DDR, is there any data to show what the performance impact is with the caches DISABLED?

Thanks!

[joanxie]

you can SCB_DisableDCache (void), SCB_DisableICache (void) and SCB_EnableDCache (void), SCB_EnableICache (void) in the CMISI of SDK, pls refer to the link as below:

"https://siliconlabs.github.io/Gecko_SDK_Doc/CMSIS/Core/html/group___dcache__functions__m7.html"

refer to the reference manual, If the I-cache is enabled, there will be a slight performance degradation (based on not cache-enabled), with no other system implications