ERR009165 on i.MX6UL(L)

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ERR009165 on i.MX6UL(L)

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ceggers
Contributor IV

The current IMX6ULLCE.pdf (Rev. 2) adds ERR009165. But in his recent SPI/SDMA patch series, Robin Gong states that i.MX6ULL is not affected:

There is ecspi ERR009165 on i.mx6/7 soc family, which cause FIFO transfer to be send twice in DMA mode.

...

The issue should be exist on all legacy i.mx6/7 soc family before i.mx6ul. NXP fix this design issue from i.mx6ul, so newer chips including i.mx6ul/ 6ull/6sll do not need this workaroud anymore. All other i.mx6/7/8 chips still need this workaroud.

...

v3: 1.Confirm with design team make sure ERR009165 fixed on i.mx6ul/i.mx6ull /i.mx6sll, not fixed on i.mx8m/8mm and other i.mx6/7 legacy chips.

So it sounds like the errata sheet is wrong. Can anyone from NXP please confirm this?

regards,
Christian

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jimmychan
NXP TechSupport
NXP TechSupport

Hello @ceggers ,

 

I got the confirmation:

Yes, NXP i.mx6ul/ 6ull/6sll/6ulz do not need this workaround anymore.

Internal ticket submitted and Doc team will update the related errata document later.

 

Best regards,

Jimmy

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jimmychan
NXP TechSupport
NXP TechSupport

Hello @ceggers ,

 

I got the confirmation:

Yes, NXP i.mx6ul/ 6ull/6sll/6ulz do not need this workaround anymore.

Internal ticket submitted and Doc team will update the related errata document later.

 

Best regards,

Jimmy

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jimmychan
NXP TechSupport
NXP TechSupport

I will check this for you.

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