EPIT support IMX6SX

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EPIT support IMX6SX

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alancasinelli
Contributor II

Hello everyone,
I'm starting developing an application on an imx6sx-sabre-sd like board. I need to collect data from an adc converter every 3microseconds through using an SPI connection.
My kernel version is linux 3.10.53. I've already read this thread: GPT as system timer, EPIT as user timer, but the boot will hang at "Starting Kernel...".

I've also tried to use the timer linux has to offer, but they really can't meet the requirements i need.

 

Am I missing something obvious?

 

You can find attached the patch I made based on the thread i quoted, and the u-boot log.

 

 

Thanks for your help.

 

EDIT:
I actually made the EPIT working by deleting every reference to one of the epit timers in clk-imx6sx.c. Now i can see the timer ticking downward to 0 and then reset to the value in the LR Register. I also enabled the OCIEN bit in the epit.c. Still I cannot seem to generate an interrupt as the gpio I'm trying to drive is not toggling. Also if I use memtool on the address 0x20d4000 (the epit2 register) I can see that the OCIEN bit is disabled. I'll keep digging into it and edit if I have new informations.

Original Attachment has been moved to: 0001-Add-epit-timer-support.patch.zip

Original Attachment has been moved to: u-boot-log.txt.zip

Labels (4)
4 Replies

139 Views
zvonimirmandi_
Contributor II

Did you have to make any changes to clock setup in Clock Controller Module to get 66 MHz as source clock for EPIT?

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139 Views
alancasinelli
Contributor II

Yes, i did.
I had to change the perclk_clk_sel bit in order to switch from the osc (24MHz) to the ipg_clk. The bit is located in the CCM_CSCMR1 register.
The file is arch/arm/mach-imx/clk-imx6sx.c. Edit the line:

/* set perclk to from OSC */

imx_clk_set_parent(clks[IMX6SX_CLK_PERCLK_SEL], clks[IMX6SX_CLK_OSC]);

to

/* set perclk to from IPG */

imx_clk_set_parent(clks[IMX6SX_CLK_PERCLK_SEL], clks[IMX6SX_CLK_IPG]);

139 Views
alejandrolozan1
NXP Employee
NXP Employee

Hi,

Have you identified if the OCIEN bit is just not modified or maybe some other process changed it?

/Alejandro

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139 Views
alancasinelli
Contributor II

Hi,

Sorry for the late reply, but I still haven't figured it out. Since I had a very limited time to debug the source code, I decided to move the time critical section of my application to the m4 core. Once I'll have enough spare time to test it, I'll update the post.

Thanks for your help.