Hi Yite,
TCE Underrun in EPDC, is caused by a corner condition: when the LUT[n] finished waveform loading but still working on WB processing, the LUT[n+1:15] waveform loading will be hold. It will be triggered when the working buffer processing time for LUT[n] spans over 2 blanking periods.
One frame scan of data will be corrupted on the frame in which the TCE underrun occurred. All subsequent frames will be correct.
The issue may be resolved by implementing one or all of the below workarounds: 1. When update is submitted, ensure the LUT acquires a higher LUT number than current active LUTs. — Order— LUT[0], LUT[1], LUT[15] — If LUT[15] is in use, TCE Underrun could still occur if new update is sent. 2. Ignore TCE Underrun IRQ — If TCE Underrun occurs, EPD hardware will continue to complete the update. — On frame where TCE Underrun occurs, the frame's data will be corrupted. All pixels will receive the last value in the FIFO. The rest of frames for an update are accurate. 3. Time update request with Frame End IRQ — If the update is submitted to the EPD, just after the VSCAN hold off, it will allow for ~2 full frames or over 23.4 mS to complete WB preprocessing for an 85-Hz panel. 4. Increase DRAM bandwidth to ensure the working buffer processing finishes within 1 frame scan. — For example, if the TCE Underrun occurs when the DRAM clock = 160 MHz, increase the DRAM clock to 200 MHz.
Latest Android BSPs versions implemented the workaround already. However looks like is not implemented to 4.0.x
Hope this helps.
