ENET_REF_CLK for I.MX6QuadPlus

[takayuki_ishii]

Hello

My customer use i.MX6Quad Plus with PCIe and gigabit-ethernet.

In migration guide(EB810) section 13 Peripherals,

it say that 

• Added a mux to the ENET reference clock to enable clocking direct from ENET PLL. In i.MX 6Dual/6Quad, the reference clock must be sourced from ENET_TX_CLK pad.

But I can not find a difference in Reference Manual.

  1) Is it meen that register setting is not changed, but it not request a external connection between ENET_REF_CLK

       and GPIO_16. is it correct?

The other hand, 

I think that it need not only frequency stability but also duty-cycle,

because RGMII interface use both edge of reference clocks for data and control.

(Reference manual section 23.6.18.2 RGMII interface).

But it is not cleared in datasheet.

I show following community threads,

ENET_REF_CLK (ball V22) duty-cycle requirements on i.MX6 

i.MX6Q ENET.REF_CLK input 

  2) Which is correct requirement of frequency stability, +-50ppm or +-25ppm?

  3) How about duty-cycle requirement. 45% - 55% is correct? or 48% - 52% is requested?

Best regards,

Ishii.

[takayuki_ishii]

Hello, Gusarambula

Thank you for your kindly support.

I will ask it to my customer.

Best regards,

Ishii.

[gusarambula]

Hello Takayuki Ishii,

(1) You are correct, the external connection required to route the clock from GPIO_16 to ENET_REF_CLK is not required on the i.MX6QP.

(2) (3) I will investigate the frequency stability and duty cycle of the internally generated clock, as this is the configuration that interests you and I cannot find these numbers.

The frequency stability and duty-cycle numbers on the threads were a recommendation but I think they were not the actual numbers of the clock signal generated by the i.MX6.

I’ll let you know as soon as I have more information.

Regards,

[b50231katsuhiro]

Hi　gusarambula‌

Could you please follow up?

if you don't have update yet, could you please let us know currently status?

Best Regards

Atsumi

[gusarambula]

Hello Atsumi,

My apologies.

The answer is to set GPR5 bit 9 to select internal 125mhz clock from ENET PLL.

However, we do not have the information regarding questions (2) and (3). I'm asking again. I'll let you know when I have more information.

Regards,

[gusarambula]

Hello Takayuki Ishii,

The recommendation I received was to use good (25-50 ppm) frequency stability and 45%~55% & duty cycle clock source. The frequency stability will affect the performance of the Ethernet module so a better stability will provide better performance up to a point. If you could use around 25ppm would be optimal but 50ppm should also work okay.

I hope this information helps!

Regards,

[takayuki_ishii]

Hello Gusarambula,

Thank you for your response.

The reason why I am asking about (2)(3) are my customer is connect from clkout of external PHY

to ENET_REF_CLK.

But duty-cycle of external-PHY clkou is moved more than 45% - 55%.

To decide is it OK or not, they are requesting a recommendation value of it.

I am waiting for your additional information.

Best regards,

Ishii.

[takayuki_ishii]

Hello Gusarambula,

Can I get some additional information about it?

I am looking forward to hearing from you.

Best regards,

Ishii