EIM read hold time with continuous BCLK

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EIM read hold time with continuous BCLK

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Contributor III

On i.MX6 DualLight we are using synchronous EIM accesses with continuous BCLK @104MHz to talk to an FPGA.  We have a setup on the board that seems to work over temperature in testing.  Looking at the FPGA timing reports, if the FPGA is in best case process corner it does not meet the 2ns hold time (WE19, figure 15, section 4.9.3.3 of datasheet Document Number: IMX6SDLCEC).

Are the setup/hold timing numbers correct for continuous BCLK where there is a DLL in the i.MX6 to lock to the read clock?

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NXP TechSupport
NXP TechSupport

Hi Andrew

please check sect.22.5.1 Continuous BCLK

i.MX6SDL Reference Manual

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SDLRM.pdf

Best regards
igor
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Contributor III

That section doesn't answer my question.  I have read that section and we have implemented those steps, but there are no timing parameters.

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NXP TechSupport
NXP TechSupport

answer is that 2ns hold time (WE19) should be followed.

I am afraid there are no guidelines for changing it using dll.

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