EIM in iMX7D in Multiplexed synchronous Read/Write mode

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EIM in iMX7D in Multiplexed synchronous Read/Write mode

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bipin7301
Contributor II

Hi,

I am trying to run the EIM interface in 16 bit Multiplexed synchronous(Burst) mode( to interface EIM with FPGA ). Please find the source code below:

  1. // WEIM clock root and clock gate registers
  2. #define CCM_BASE_ADDRESS 0x30380000
  3. #define CCM_CCGR22 0x30384160
  4. #define CCM_TARGET_ROOT83 0x3038A980
  5. /* WEIM registers */
  6. typedef struct
  7. {
  8. UINT32 EIM_CS0GCR1;
  9. UINT32 EIM_CS0GCR2;
  10. UINT32 EIM_CS0RCR1;
  11. UINT32 EIM_CS0RCR2;
  12. UINT32 EIM_CS0WCR1;
  13. UINT32 EIM_CS0WCR2;
  14. UINT32 EIM_CS1GCR1;
  15. UINT32 EIM_CS1GCR2;
  16. UINT32 EIM_CS1RCR1;
  17. UINT32 EIM_CS1RCR2;
  18. UINT32 EIM_CS1WCR1;
  19. UINT32 EIM_CS1WCR2;
  20. UINT32 EIM_CS2GCR1;
  21. UINT32 EIM_CS2GCR2;
  22. UINT32 EIM_CS2RCR1;
  23. UINT32 EIM_CS2RCR2;
  24. UINT32 EIM_CS2WCR1;
  25. UINT32 EIM_CS2WCR2;
  26. UINT32 EIM_CS3GCR1;
  27. UINT32 EIM_CS3GCR2;
  28. UINT32 EIM_CS3RCR1;
  29. UINT32 EIM_CS3RCR2;
  30. UINT32 EIM_CS3WCR1;
  31. UINT32 EIM_CS3WCR2;
  32. UINT32 EIM_CS4GCR1;
  33. UINT32 EIM_CS4GCR2;
  34. UINT32 EIM_CS4RCR1;
  35. UINT32 EIM_CS4RCR2;
  36. UINT32 EIM_CS4WCR1;
  37. UINT32 EIM_CS4WCR2;
  38. UINT32 EIM_CS5GCR1;
  39. UINT32 EIM_CS5GCR2;
  40. UINT32 EIM_CS5RCR1;
  41. UINT32 EIM_CS5RCR2;
  42. UINT32 EIM_CS5WCR1;
  43. UINT32 EIM_CS5WCR2;
  44. UINT32 EIM_WCR;
  45. UINT32 EIM_DCR;
  46. UINT32 EIM_DSR;
  47. UINT32 EIM_WIAR;
  48. UINT32 EIM_EAR;
  49. }tEIM_CSP_WEIM_REGS, *ptEIM_CSP_WEIM_REGS;
  50. //-----------------------------------------------------------------------------
  51. // Configure the IOs for the iMX7 EIM bus
  52. /// @param[in] hGpio handle received from Gpio_Init()
  53. /// @retval TRUE Success
  54. /// @retval FALSE Failure
  55. BOOL Eim_ConfigureIos(HANDLE hGpio)
  56. {
  57. int i;
  58. BOOL fSuccess = TRUE;
  59. const uIo eimIo[] =
  60. {
  61. COLIBRI_PIN( 89), // RW
  62. COLIBRI_PIN( 91), // OE
  63. COLIBRI_PIN(105), // CS0_B
  64. COLIBRI_PIN(150), // LBA_B
  65. COLIBRI_PIN(152), // BCLK
  66. COLIBRI_PIN(111), // AD0
  67. COLIBRI_PIN(113), // AD1
  68. COLIBRI_PIN(115), // AD2
  69. COLIBRI_PIN(117), // AD3
  70. COLIBRI_PIN(119), // AD4
  71. COLIBRI_PIN(121), // AD5
  72. COLIBRI_PIN(123), // AD6
  73. COLIBRI_PIN(125), // AD7
  74. COLIBRI_PIN(110), // AD8
  75. COLIBRI_PIN(112), // AD9
  76. COLIBRI_PIN(114), // AD10
  77. COLIBRI_PIN(116), // AD11
  78. COLIBRI_PIN(118), // AD12
  79. COLIBRI_PIN(120), // AD13
  80. COLIBRI_PIN(122), // AD14
  81. COLIBRI_PIN(124) // AD15
  82. };
  83. /// The EIM functionality is on Alternate Function 4 for all EIM pins.
  84. for (i = 0; i < _countof(eimIo); i++)
  85. fSuccess &= Imx7Gpio_SetConfigString(hGpio, eimIo[i], NULL, L"AltFn=4", StoreVolatile);
  86. return fSuccess;
  87. }
  88. //*****************************************************************************
  89. /// Main function
  90. /// @param[in] argc number of command line arguments
  91. /// @param[in] argv array containing command line arguments
  92. /// @retval 1 Success
  93. /// @retval 0 Failure
  94. int wmain(int argc, _TCHAR* argv[])
  95. {
  96. BOOL fSuccess = TRUE;
  97. HANDLE hMap;
  98. HANDLE hGpio;
  99. volatile ptEIM_CSP_WEIM_REGS pEimReg;
  100. volatile DWORD *clkRegs;
  101. volatile DWORD tmp;
  102. volatile UINT16 *extBus;
  103. volatile DWORD *targetAddr;
  104. UINT16 i;
  105. UINT16 buff[ ] = { 0xAA,0x11,0x22,0x77,0x33,0x44,0x55,0x66 };
  106. // Enable EIM Clock,
  107. hMap = Map_Init();
  108. clkRegs = (DWORD* )Map_MapMemory(CCM_BASE_ADDRESS, 0x10000);
  109. targetAddr = clkRegs + (CCM_CCGR22 - CCM_BASE_ADDRESS)/4;
  110. *targetAddr &= ~0xFFFFFFFF;
  111. targetAddr = clkRegs + (CCM_TARGET_ROOT83 - CCM_BASE_ADDRESS)/4;
  112. *targetAddr |= 0x16030000; // 125MHz/4
  113. targetAddr = clkRegs + (CCM_CCGR22 - CCM_BASE_ADDRESS)/4;
  114. *targetAddr |= 0x03;
  115. // configure EIM GPIOs
  116. hGpio = Imx7Gpio_Init(NULL);
  117. fSuccess &= Eim_ConfigureIos(hGpio);
  118. fSuccess &= Imx7Gpio_Deinit(hGpio);
  119. // Configure CS0 properties for multiplexed, asynchronous operation
  120. pEimReg = (ptEIM_CSP_WEIM_REGS)Map_MapMemory(0x30BC0000, 0x1000);
  121. pEimReg->EIM_WIAR &= ~( 1 << 4 );
  122. pEimReg->EIM_CS0GCR1 = 0x0011013F;
  123. pEimReg->EIM_CS0GCR2 = 0x00001000;
  124. pEimReg->EIM_CS0RCR1 = 0x01000000;
  125. pEimReg->EIM_CS0RCR2 = 0x00000000;
  126. pEimReg->EIM_CS0WCR1 = 0x01000000;
  127. pEimReg->EIM_CS0WCR2 = 0x00000000;
  128. pEimReg->EIM_WCR |= ( 1 << 3 );
  129. pEimReg->EIM_WIAR |= ( 1 << 4 );
  130. printf("CSxGCR1 main reg: 0x%08X\n",pEimReg->EIM_CS0GCR1);
  131. printf("CSxGCR2 main reg: 0x%08X\n",pEimReg->EIM_CS0GCR2);
  132. printf("CSxRCR1 main reg: 0x%08X\n",pEimReg->EIM_CS0RCR1);
  133. printf("CSxRCR2 main reg: 0x%08X\n",pEimReg->EIM_CS0RCR2);
  134. printf("CSxWCR1 main reg: 0x%08X\n",pEimReg->EIM_CS0WCR1);
  135. printf("CSxWCR2 main reg: 0x%08X\n",pEimReg->EIM_CS0WCR2);
  136. printf("WCR main reg: 0x%08X\n",pEimReg->EIM_WCR);
  137. printf("WIAR main reg: 0x%08X\n",pEimReg->EIM_WIAR);
  138. printf("DCR main reg: 0x%08X\n",pEimReg->EIM_DCR);
  139. printf("DSR main reg: 0x%08X\n",pEimReg->EIM_DSR);
  140. // Access memory at CS0 address.
  141. // The address range for nCS0 is 0x28000000 to 0x28FFFFFF (128MB).
  142. // However, we map only 64kB here.
  143. extBus =(UINT16* )Map_MapMemory(0x28000000, 0x5000);
  144. while(1)
  145. {
  146. memcpy( (UINT16*)extBus, buff, sizeof( buff ) );
  147. }
  148. return 1;
  149. }

As per my understanding when using burst mode with every address assertion an address and then a burst of data(8 Words in my case) will be sent on EIM bus and then process repeats as I am running a while loop. However this is not a happening in my case. I am not able to see this behaviour. Data is not coming in burst and Address, CS and RW signals are not as per configuration.

There are few queries for better understanding of the interface:

1. Is there difference between Synchronous mode and Burst mode ?

2. Is there any initialisation sequence for continuous BCLK Multiplexed synchronous mode ?

3. In case of fix latency mode all the wait states are ignored( like WWSC/RWSC) ?

4. Start address of CS0 is 0x28000000, I haven't found it in iMX7D reference guide, From where i can find the addresses of all the chip selects ?

Regards

Bipin Kumar

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Bipin

>1. Is there difference between Synchronous mode and Burst mode ?

yes

>2. Is there any initialisation sequence for continuous BCLK Multiplexed synchronous mode ?

better description can be found in sect.22.5.1 Continuous BCLK i.MX6SDL Reference Manual

http://www.nxp.com/assets/documents/data/en/reference-manuals/IMX6SDLRM.pdf

>3. In case of fix latency mode all the wait states are ignored( like WWSC/RWSC) ?

please check sect.9.7.5.9 WAIT_B Signal, RWSC and WWSC bit fields Usage :

For devices which .. have a fixed latency ability, the RFL and
WFL bits may be set for internal calculation regarding BCLK cycles penalty until data is
valid (memory initial access time). For this mode, RWSC/ WWSC indicates when the
data is ready for sampling by the controller (read access) or the external device (write
access).

4. Start address of CS0 is 0x28000000, I haven't found it in iMX7D reference guide,
>From where i can find the addresses of all the chip selects ?

please check sect.2.1.2 Cortex-A7 Memory Map p.237,
sect.8.2.4.2 GPR1 General Purpose Register (IOMUXC_GPR_GPR1)
i.MX7D Reference Manual
https://www.nxp.com/files-static/32bit/doc/ref_manual/IMX7DRM.pdf 

Best regards
igor
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bipin7301
Contributor II

Thanks for the Response IGOR.

1. I have posted a code in my previous post and wrote my understanding of the behaviour of the code. Can you please comment on my understanding ?

2. Can you elaborate on the difference between Synchronous and Burst mode ?

   and As you said these are two different mode then Is it possible to have Multiplexed Synchronous mode( without BCLK ) ? and if it is possible then Which signal will be used to synchronise ?

3. For Continuous BCLK, you have referred iMX6. Is it valid for iMX7 also ?

    As I have followed the initialisation sequence mentioned in i.MX6SDL Reference Manual but in Step 6 DLL does not Lock(  Both bit 0 and bit 1 of EIM_DSR Register stay un-asserted ).

4. We are trying to configure the EIM module but after configuration EIM registers does not read as Configured. 

Earlier we have worked on iMX53, in that we had to enable the Slow clock before EIM register settings.

So Do we need to do it in iMX7 also ? And if yes then How to enable the slow clock in iMX7 ? As there is only one CCGR register for EIM i.e. CCGR22.

Regards

Bipin

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Bipin

NXP has special service for helping customers to port software and reviewing their codes.

NXP Professional Services | NXP 

Best regards
igor

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Bipin

> difference between Synchronous and Burst mode ?

suggest to check:

i.MX6 maximum EIM burst length and performance  

How to configure IMX6Q EIM Burst Synchronous to one BCLK one data? 

>For Continuous BCLK, you have referred iMX6. Is it valid for iMX7 also ?

yes

for 4) one can attach jtag debugger and test with it.

Best regards
igor

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