Does the iMX53 support dynamic ODT on DDR3 RAM?

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Does the iMX53 support dynamic ODT on DDR3 RAM?

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docobo
Contributor I

Does the iMX53 support dynamic ODT on DDR3 RAM?  I can't see anything in the datasheet so assume it doesn't though i thought i'd try here as well.

Thanks,

Tim

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Yuri
NXP TechSupport
NXP TechSupport

The i.MX53 memory controller does not support such features, sorry.


Have a great day,
Yuri

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Yuri
NXP TechSupport
NXP TechSupport


  Yes, i.MX53 supports ODT when accessed DRAM. ODT may be enabled / disabled,
resistance values may be configured, may be activated during read or write, may be used
to be active for other CS or for the active CS.  Please refer to sections 28.121.23 [PHY ODT
Control Register (ESDCTL_ODTCTRL)] and  28.121.3 [ESDCTL ODT Timing Control Register
(ESDCTL_ESDOTC)] of the iMX53RM, Rev. 2.1, 06/2012.


Have a great day,
Yuri

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docobo
Contributor I

Thanks for your reply Yuri.

There is a difference between ODT and dynamic ODT.  I understand that the iMX53 supports ODT on the RAM chip but I want to know if it supports dynamic ODT.

From the Micron MT41J256M16RE-15E datasheet (the RAM we are using):

"In certain application cases, and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command, essentially changing the ODT termination on the fly. With dynamic ODT RTT(WR)) enabled, the DRAM switches from nominal ODT RTT,nom) to dynamic ODT RTT(WR)) when beginning a WRITE burst and subsequently switches back to nominal ODT RTT,nom) at the completion of the WRITE burst. This requirement is supported by the dynamic ODT feature, as described below."

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Yuri
NXP TechSupport
NXP TechSupport

The i.MX53 memory controller does not support such features, sorry.


Have a great day,
Yuri

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