Hi ,
As per the IMX reference Manual , section 8.5.5.2 ,
"As part of the NAND media initialization, the ROM driver uses safe NAND timings to
search for a Firmware Configuration Block (FCB) that contains the optimum NAND
timings, page address of Discovered Bad Block Table (DBBT) Search Area and start
page address of primary and secondary firmware "
So as per my understanding , Interrupt Vector table should be part of the FCB data structure . Please let me know if it is not so.
Regards,
Aditya Nagal
Hi Aditya
no, Interrupt Vector table is not part of the FCB data structure.
Details can be found in Boot Chapter of processor Reference Manual.
Best regards
igor
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