Does iMX6 MIPI CSI-2 support camera sensors with "non-continuous" clock mode?

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Does iMX6 MIPI CSI-2 support camera sensors with "non-continuous" clock mode?

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OmarPighi
Contributor I

Hi everybody,

I'm going to start my custom mipi camera sensor.

My transmitter supports "non-continuous" clock mode (clock lane goes in LP11 during H and V blanking).

I made a test with SabreLite and ov5640 mipi: connecting oscilloscope on sensor output clock, it looks continuous every time (exept when it leaves power down state).

Do you know if iMX6 MIPI CSI-2 supports "non-continuous" clock mode?

Looking on "MIPI Alliance Specification for Camera Serial Interface 2 (CSI-2)", I found the following sentence:

"All CSI-2 transmitter and receivers shall support continuous clock behaviour on the Clock Lane, and optionally may support non-continuous clock behaviour".


many thanks.

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SergioSolis
NXP Employee
NXP Employee

Hello Omar,

As the alliance paper says: in order to get non-continuous clock behavior the Clock Lane enters the LP-11 state between the transmission of data packets.

So to answer your question, yes, it can support non-continuous clock mode, but you would have to implement it.


Have a great day,
Sergio

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OmarPighi
Contributor I

Good morning Sergio,

many thanks for your answer.

Could you give me some suggestions or some documentation regarding how to implement it?

Let me explain why I'm interested on non-continuous clock mode.

My camera sensor has a parallel bus that is converted in MIPI by an FPGA. The Bridge IP Core that Lattice give to me produce a MIPI with non-continuous clock. I'm sure that is possible to change the clock mode by Tx side... but I'm a dummy in verilog programming. So, if it's possible, I preferere to do it from Rx side.

Thank you in advance for the support that you will want to give me.

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SergioSolis
NXP Employee
NXP Employee

Hello Omar,

Unfortunately we do not have a document that explains how to implement it.

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OmarPighi
Contributor I

Hello Sergio,

thank you anyway. I worked with the engineer that manage the source (as I say you before, I'm not an expert in FPGA) and we are able now to produce a mipi stream with continuous clock. I saw the first image!!

I didn't fix all my issues but, right now, the most important thing is that the low level is ok. Now, I have some problems on data path MIPI_PHY --> gasket --> CSI --> SMFC --> IDMAC and I get an image with wrong sizes. The image should be a 1280x960pix but I captured four 640x480. I think there is something wrong in the BPP,NPB setting. I'm going to read some post. If I'll not be able to find a solution, probably I'll need to post a new thread.

Thank you.

Quad.bmp

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