Does i.MX8MQ GIC have legacy modes?What is the address of GIC CPU interface?

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Does i.MX8MQ GIC have legacy modes?What is the address of GIC CPU interface?

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pengcheng
Contributor III

What is i.MX8MQ GIC versoin number? GIC500?

Does i.MX8MQ GIC have legacy modes?

What is the memory address of GIC CPU interface?

Thanks!

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pengcheng
Contributor III

Anyone can help me? Thanks!

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Yuri
NXP Employee
NXP Employee

Hello,

According to the ARM processor documentation CBAR_EL1 register "holds the physical
base address of the memory-mapped GIC CPU interface registers”.

ARM Information Center 

Regards,

Yuri.

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pengcheng
Contributor III

I can detect imx8mq has GIC-500 according to IIDR and PIDR register.

And did not support memory mapped CPU interface by testing other registers.

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pengcheng
Contributor III

Recently I found that, software working in EL3 can change the SRE and ARE bit.

So if I want to use legacy mode for non-SRE, I must know the memory address of CPU-interface.

GICv3 is designed by ARM, that is right, but  it is connect to NOC by NXP.

NXP should know the memory address of CPU-interface.

My question is I want to know the memory address of CPU-interface to use the legacy mode.

So I reopen this issue.

Thanks!

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igorpadykov
NXP Employee
NXP Employee

Hi Peng

please refer to sect.4.1.4 Platform sub-blocks i.MX8MDQ Reference Manual

and arm documentation

ARM Information Center 

https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf

core revision is r0p4-51rel0, as described in sect.4.1.2 Configuration.

Best regards
igor
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pengcheng
Contributor III

Hi igor,

Thanks!

But you don't answer my questions. I knew the GIC is GIC v4.

But I do not want to use <system registers enable> method, instead I want to use the legacy mode which will operates CPU interface by using memory-mapped regions.

So, my main question is:

1. Does i.MX8MQ GIC have legacy modes?

2. What is the memory-mapped address of GIC CPU interface?

BR,

Peng

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igorpadykov
NXP Employee
NXP Employee

Hi Peng

GIC is module designed by arm, suggest to post it on arm forum.

Arm Development Platforms forum - Arm Development Platforms - Arm Community 

Best regards
igor

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pengcheng
Contributor III

Hi igor,

Thanks!

I know GIC is designed by arm, but some parts are implemented by vendors. That is why I want to know which type is this GIC? GIC500?GIC600?

For example:

“Whether a GICv3 implementation includes a mechanism to support legacy operation of physical interrupts is
IMPLEMENTATION DEFINED.”

And also I think memory map is also implemented by vendors, ARM only support the register offset which are based on that memory block. 

Am I right?

BR,

Peng

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igorpadykov
NXP Employee
NXP Employee

GIC400 and its address is given in sect.2.1.2 Cortex-A53 Memory Map i.MX8MDQ Reference Manual
https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf

Best regards
igor

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pengcheng
Contributor III

Hi igor,

Thanks!

1. I don't think GIC400 is correct.

In page 565 of IMX8MDQLQRM. It said:

"The Cortex-A53 processor implements the GIC CPU interface as described in the
Generic Interrupt Controller (GICv4) architecture."

I think GIC400 is not GICv4 based. 

2. Also the memory map only refer that the GIC block.

"3880_0000 388F_FFFF GIC 1MB GIC REG"

But doesn't mention the address of CPU interface. And I can't find it in the linux code ether. I know it can be accessed by system register, but I still want to use legacy mode.So I want to know the address of CPU interface.

BR,

Peng

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