Does anybody know which peripherals are assigned to the AIPSTZx_OPACRy fields?

[ffm]

The iMX6 DQ Reference Manual doesn't say anything about it. With the information from chapter 13 that each AIPS supports up to 32 16-Kbyte peripherals plus 2 global peripheral spaces one can try guessing from the memory map given in chapter 2 but with no confidence. Anyway, the addresses for AIPS1 and AIPS2 given in the register map in chapter 13 are wrong. The correct ones can be found in the memory map in chapter 2.

[ffm · Accepted solution]

Hi all,

I got a response to my SR from Freescale, which more or less gave the answers. So I post here a version created by myself and as suggested to Freescale of those parts (Tables 2-2 and 2-3 in RM):

Start Address	End Address	Region	NIC Port	Size
020FC000	020FFFFF	AIPS-1 (OPACR31)	Reserved	16 KB
020F8000	020FBFFF	AIPS-1 (OPACR30)	Reserved	16 KB
020F4000	020F7FFF	AIPS-1 (OPACR29)	Reserved	16 KB
020F0000	020F3FFF	AIPS-1 (OPACR28)	Reserved	16 KB
020EC000	020EFFFF	AIPS-1 (OPACR27)	SDMA	16 KB
020E8000	020EBFFF	AIPS-1 (OPACR26)	DCIC2	16 KB
020E4000	020E7FFF	AIPS-1 (OPACR25)	DCIC1	16 KB
020E0000	020E3FFF	AIPS-1 (OPACR24)	IOMUXC	16 KB
020DC2B0	020DFFFF	AIPS-1 (OPACR23)	Reserved	15696 B
020DC2A0	020DC2AF		PGC_CPU	16 B
020DC270	020DC29F		Reserved	48 B
020DC260	020DC26F		PGC_GPU	16 B
020DC1C4	020DC25F		Reserved	156 B
020DC180	020DC1C3		DVFS	68 B
020DC028	020DC17F		Reserved	344 B
020DC000	020DC027		GPC	40 B
020D8000	020DBFFF	AIPS-1 (OPACR22)	SRC	16 KB
020D4000	020D7FFF	AIPS-1 (OPACR21)	EPIT2	16 KB
020D0000	020D3FFF	AIPS-1 (OPACR20)	EPIT1	16 KB
020CC000	020CFFFF	AIPS-1 (OPACR19)	SNVS_HP	16 KB
020CB000	020CBFFF	AIPS-1 (OPACR18)	Reserved	4 KB
020CA000	020CAFFF		USBPHY2	4 KB
020C9000	020C9FFF		USBPHY1	4 KB
020C8000	020C8FFF		CCM_ANALOG	4 KB
020C4000	020C7FFF	AIPS-1 (OPACR17)	CCM_DIGITAL	16 KB
020C0000	020C3FFF	AIPS-1 (OPACR16)	WDOG2	16 KB
020BC000	020BFFFF	AIPS-1 (OPACR15)	WDOG1	16 KB
020B8000	020BBFFF	AIPS-1 (OPACR14)	KPP	16 KB
020B4000	020B7FFF	AIPS-1 (OPACR13)	GPIO7	16 KB
020B0000	020B3FFF	AIPS-1 (OPACR12)	GPIO6	16 KB
020AC000	020AFFFF	AIPS-1 (OPACR11)	GPIO5	16 KB
020A8000	020ABFFF	AIPS-1 (OPACR10)	GPIO4	16 KB
020A4000	020A7FFF	AIPS-1 (OPACR9)	GPIO3	16 KB
020A0000	020A3FFF	AIPS-1 (OPACR8)	GPIO2	16 KB
0209C000	0209FFFF	AIPS-1 (OPACR7)	GPIO1	16 KB
02098000	0209BFFF	AIPS-1 (OPACR6)	GPT	16 KB
02094000	02097FFF	AIPS-1 (OPACR5)	CAN2	16 KB
02090000	02093FFF	AIPS-1 (OPACR4)	CAN1	16 KB
0208C000	0208FFFF	AIPS-1 (OPACR3)	PWM4	16 KB
02088000	0208BFFF	AIPS-1 (OPACR2)	PWM3	16 KB
02084000	02087FFF	AIPS-1 (OPACR1)	PWM2	16 KB
02080000	02083FFF	AIPS-1 (OPACR0)	PWM1	16 KB
0207C000	0207FFFF	AIPS-1	AIPS1	16 KB
02040000	0207BFFF	AIPS-2 Global Module Enable (OPACR33)	VPU	240 KB
0203C000	0203FFFF	AIPS-2 Global Module Enable (OPACR32)	SPBA	16 KB
02038000	0203BFFF		Reserved	16 KB
02034000	02037FFF		ASRC	16 KB
02030000	02033FFF		SSI3	16 KB
0202C000	0202FFFF		SSI2	16 KB
02028000	0202BFFF		SSI1	16 KB
02024000	02027FFF		ESAI	16 KB
02020000	02023FFF		UART1	16 KB
0201C000	0201FFFF		Reserved	16 KB
02018000	0201BFFF		eCSPI5	16 KB
02014000	02017FFF		eCSPI4	16 KB
02010000	02013FFF		eCSPI3	16 KB
0200C000	0200FFFF		eCSPI2	16 KB
02008000	0200BFFF		eCSPI1	16 KB
02004000	02007FFF		SPDIF	16 KB
02000000	02003FFF		Reserved	16 KB

Start Address	End Address	Region	NIC Port	Size
021FC000	021FFFFF	AIPS-2 (OPACR31)	Reserved	16 KB
021F8000	021FBFFF	AIPS-2 (OPACR30)	Reserved	16 KB
021F4000	021F7FFF	AIPS-2 (OPACR29)	UART5	16 KB
021F0000	021F3FFF	AIPS-2 (OPACR28)	UART4	16 KB
021EC000	021EFFFF	AIPS-2 (OPACR27)	UART3	16 KB
021E8000	021EBFFF	AIPS-2 (OPACR26)	UART2	16 KB
021E4000	021E7FFF	AIPS-2 (OPACR25)	VDOA	16 KB
021E0000	021E3FFF	AIPS-2 (OPACR24)	MIPI_DSI	16 KB
021DC000	021DFFFF	AIPS-2 (OPACR23)	MIPI_CSI	16 KB
021D8000	021DBFFF	AIPS-2 (OPACR22)	AUDMUX	16 KB
021D4000	021D7FFF	AIPS-2 (OPACR21)	TZASC2	16 KB
021D0000	021D3FFF	AIPS-2 (OPACR20)	TZASC1	16 KB
021CC000	021CFFFF	AIPS-2 (OPACR19)	Reserved	16 KB
021C8000	021CBFFF	AIPS-2 (OPACR18)	Reserved	16 KB
021C4000	021C7FFF	AIPS-2 (OPACR17)	Reserved	16 KB
021C0000	021C3FFF	AIPS-2 (OPACR16)	CSU	16 KB
021BC000	021BFFFF	AIPS-2 (OPACR15)	OCOTP_CTRL	16 KB
021B8000	021BBFFF	AIPS-2 (OPACR14)	EIM	16 KB
021B4000	021B7FFF	AIPS-2 (OPACR13)	MMDC1	16 KB
021B0000	021B3FFF	AIPS-2 (OPACR12)	MMDC0	16 KB
021AC000	021AFFFF	AIPS-2 (OPACR11)	ROMCP	16 KB
021A8000	021ABFFF	AIPS-2 (OPACR10)	I2C3	16 KB
021A4000	021A7FFF	AIPS-2 (OPACR9)	I2C2	16 KB
021A0000	021A3FFF	AIPS-2 (OPACR8)	I2C1	16 KB
0219C000	0219FFFF	AIPS-2 (OPACR7)	uSDHC4	16 KB
02198000	0219BFFF	AIPS-2 (OPACR6)	uSDHC3	16 KB
02194000	02197FFF	AIPS-2 (OPACR5)	uSDHC2	16 KB
02190000	02193FFF	AIPS-2 (OPACR4)	uSDHC1	16 KB
0218C000	0218FFFF	AIPS-2 (OPACR3)	MLB150	16 KB
02188000	0218BFFF	AIPS-2 (OPACR2)	ENET	16 KB
02184000	02187FFF	AIPS-2 (OPACR1)	USBOH3	16 KB
02180000	02183FFF	AIPS-2 (OPACR0)	Reserved	16 KB
0217C000	0217FFFF	AIPS-2	AIPS2	16 KB
02161000	0217BFFF	AIPS-2 Global Module Enable (OPACR33)	Reserved	108 KB
02140000	02160FFF		ARM_MPCORE_DAP	132 KB
02110000	0213FFFF	AIPS-2 Global Module Enable (OPACR32)	Reserved	192 KB
02100000	0210FFFF		CAAM	64 KB

[Rob_iMX6]

Hi Frank

I've just stumbled upon the same question...

Did you get the mappings from Fresscale? If so, could you please post them here?

Thanks in advance and best regards,

-Urs

[ffm]

Hi Rob,

I did not yet get an answer from Frescale support. Otherwise I would of course have posted the mapping here to be available to the comunity. Anyway I started manually testing, which of the peripherals shows a reaction on changing the flags. It seamsthat the order of the peripherals (16K-blocks) in the memory map in chapter 2 matches the order of the OPACR registers. Currently I checked only the following peripherals:
PWM1   -> AIPSTZ1_OPACR.OPAC0
PWM2   -> AIPSTZ1_OPACR.OPAC1
GPIO1  -> AIPSTZ1_OPACR.OPAC7
GPIO2  -> AIPSTZ1_OPACR1.OPAC8
GPIO7  -> AIPSTZ1_OPACR1.OPAC13
CCM    -> AIPSTZ1_OPACR2.OPAC17
IOMUXC -> AIPSTZ1_OPACR3.OPAC24

I further guess that AIPSTZ1_OPACR3.OPAC32 and AIPSTZ1_OPACR3.OPAC33 are the so called global module enables and map to all or at least multiple of those peripherals in the memory map in chapter 2, which are stated to be AIPS-1 Global Module Enable. The question here, which I can't answer yet, is: Do all those peripherals map to AIPSTZ1_OPACR3.OPAC32 or is there a split between AIPSTZ1_OPACR3.OPAC32 and AIPSTZ1_OPACR3.OPAC33? If there is no split, which peripheral(s) map to AIPSTZ1_OPACR3.OPAC33?

Another point is, that it seams that the AIPS itself, which is also a peripheral (16K-block), has no access control.

And one more point is, that the iMX6 implements another peripheral, the so called central security unit (CSU) which has very similar purpose and features. Some of the peripherals are access controlled by both, one AIPS and the CSU, others are access controlled by the CSU only. I'm not yet sure whether peripherals exist which are access controlled only by the AIPS and I even do not know the priority/dependency of the access permission between those two control facilities (AIPS and CSU).

Regards, Frank

[Rob_iMX6]

Hi Frank

Thanks a lot for this insight, very interesting! For now I will leave accesses open, though... and come back to this mapping question later, once everything works.

Best regards,

-Urs or Rob, my middle name, as the first name is pretty unkown... :-)

[igorpadykov]

Hi Frank

suggest to create SR to tech support, this table with peripherals

will be provided. Regarding " addresses for AIPS1 and AIPS2 given in the

register map in chapter 13 are wrong" - RM Chapter description is just generic description,

specific addresses one needs to look at chapter 2.

Best regards

chip

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[ffm]

Hi chipexpert,

thanks for your answer. I will create ans SR.

Regarding the address issue: Don't you assent that in a generic desription it would be better to give just the register offsets rather than absoulute addresses?

Regards, Frank

[igorpadykov]

Hi Frank

I think yes

Best regards

chip