Does anybody know which peripherals are assigned to the AIPSTZx_OPACRy fields?

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Does anybody know which peripherals are assigned to the AIPSTZx_OPACRy fields?

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ffm
Contributor III

The iMX6 DQ Reference Manual doesn't say anything about it. With the information from chapter 13 that each AIPS supports up to 32 16-Kbyte peripherals plus 2 global peripheral spaces one can try guessing from the memory map given in chapter 2 but with no confidence. Anyway, the addresses for AIPS1 and AIPS2 given in the register map in chapter 13 are wrong. The correct ones can be found in the memory map in chapter 2.

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ffm
Contributor III

Hi all,

I got a response to my SR from Freescale, which more or less gave the answers. So I post here a version created by myself and as suggested to Freescale of those parts (Tables 2-2 and 2-3 in RM):

   

Start AddressEnd AddressRegionNIC PortSize
020FC000020FFFFFAIPS-1 (OPACR31)Reserved16 KB
020F8000020FBFFFAIPS-1 (OPACR30)Reserved16 KB
020F4000020F7FFFAIPS-1 (OPACR29)Reserved16 KB
020F0000020F3FFFAIPS-1 (OPACR28)Reserved16 KB
020EC000020EFFFFAIPS-1 (OPACR27)SDMA16 KB
020E8000020EBFFFAIPS-1 (OPACR26)DCIC216 KB
020E4000020E7FFFAIPS-1 (OPACR25)DCIC116 KB
020E0000020E3FFFAIPS-1 (OPACR24)IOMUXC16 KB
020DC2B0020DFFFFAIPS-1 (OPACR23)Reserved15696 B
020DC2A0020DC2AFPGC_CPU16 B
020DC270020DC29FReserved48 B
020DC260020DC26FPGC_GPU16 B
020DC1C4020DC25FReserved156 B
020DC180020DC1C3DVFS68 B
020DC028020DC17FReserved344 B
020DC000020DC027GPC40 B
020D8000020DBFFFAIPS-1 (OPACR22)SRC16 KB
020D4000020D7FFFAIPS-1 (OPACR21)EPIT216 KB
020D0000020D3FFFAIPS-1 (OPACR20)EPIT116 KB
020CC000020CFFFFAIPS-1 (OPACR19)SNVS_HP16 KB
020CB000020CBFFFAIPS-1 (OPACR18)Reserved4 KB
020CA000020CAFFFUSBPHY24 KB
020C9000020C9FFFUSBPHY14 KB
020C8000020C8FFFCCM_ANALOG4 KB
020C4000020C7FFFAIPS-1 (OPACR17)CCM_DIGITAL16 KB
020C0000020C3FFFAIPS-1 (OPACR16)WDOG216 KB
020BC000020BFFFFAIPS-1 (OPACR15)WDOG116 KB
020B8000020BBFFFAIPS-1 (OPACR14)KPP16 KB
020B4000020B7FFFAIPS-1 (OPACR13)GPIO716 KB
020B0000020B3FFFAIPS-1 (OPACR12)GPIO616 KB
020AC000020AFFFFAIPS-1 (OPACR11)GPIO516 KB
020A8000020ABFFFAIPS-1 (OPACR10)GPIO416 KB
020A4000020A7FFFAIPS-1 (OPACR9)GPIO316 KB
020A0000020A3FFFAIPS-1 (OPACR8)GPIO216 KB
0209C0000209FFFFAIPS-1 (OPACR7)GPIO116 KB
020980000209BFFFAIPS-1 (OPACR6)GPT16 KB
0209400002097FFFAIPS-1 (OPACR5)CAN216 KB
0209000002093FFFAIPS-1 (OPACR4)CAN116 KB
0208C0000208FFFFAIPS-1 (OPACR3)PWM416 KB
020880000208BFFFAIPS-1 (OPACR2)PWM316 KB
0208400002087FFFAIPS-1 (OPACR1)PWM216 KB
0208000002083FFFAIPS-1 (OPACR0)PWM116 KB
0207C0000207FFFFAIPS-1AIPS116 KB
020400000207BFFFAIPS-2 Global Module Enable (OPACR33)VPU240 KB
0203C0000203FFFFAIPS-2 Global Module Enable (OPACR32)SPBA16 KB
020380000203BFFFReserved16 KB
0203400002037FFFASRC16 KB
0203000002033FFFSSI316 KB
0202C0000202FFFFSSI216 KB
020280000202BFFFSSI116 KB
0202400002027FFFESAI16 KB
0202000002023FFFUART116 KB
0201C0000201FFFFReserved16 KB
020180000201BFFFeCSPI516 KB
0201400002017FFFeCSPI416 KB
0201000002013FFFeCSPI316 KB
0200C0000200FFFFeCSPI216 KB
020080000200BFFFeCSPI116 KB
0200400002007FFFSPDIF16 KB
0200000002003FFFReserved16 KB


   

Start AddressEnd AddressRegionNIC PortSize
021FC000021FFFFFAIPS-2 (OPACR31)Reserved16 KB
021F8000021FBFFFAIPS-2 (OPACR30)Reserved16 KB
021F4000021F7FFFAIPS-2 (OPACR29)UART516 KB
021F0000021F3FFFAIPS-2 (OPACR28)UART416 KB
021EC000021EFFFFAIPS-2 (OPACR27)UART316 KB
021E8000021EBFFFAIPS-2 (OPACR26)UART216 KB
021E4000021E7FFFAIPS-2 (OPACR25)VDOA16 KB
021E0000021E3FFFAIPS-2 (OPACR24)MIPI_DSI16 KB
021DC000021DFFFFAIPS-2 (OPACR23)MIPI_CSI16 KB
021D8000021DBFFFAIPS-2 (OPACR22)AUDMUX16 KB
021D4000021D7FFFAIPS-2 (OPACR21)TZASC216 KB
021D0000021D3FFFAIPS-2 (OPACR20)TZASC116 KB
021CC000021CFFFFAIPS-2 (OPACR19)Reserved16 KB
021C8000021CBFFFAIPS-2 (OPACR18)Reserved16 KB
021C4000021C7FFFAIPS-2 (OPACR17)Reserved16 KB
021C0000021C3FFFAIPS-2 (OPACR16)CSU16 KB
021BC000021BFFFFAIPS-2 (OPACR15)OCOTP_CTRL16 KB
021B8000021BBFFFAIPS-2 (OPACR14)EIM16 KB
021B4000021B7FFFAIPS-2 (OPACR13)MMDC116 KB
021B0000021B3FFFAIPS-2 (OPACR12)MMDC016 KB
021AC000021AFFFFAIPS-2 (OPACR11)ROMCP16 KB
021A8000021ABFFFAIPS-2 (OPACR10)I2C316 KB
021A4000021A7FFFAIPS-2 (OPACR9)I2C216 KB
021A0000021A3FFFAIPS-2 (OPACR8)I2C116 KB
0219C0000219FFFFAIPS-2 (OPACR7)uSDHC416 KB
021980000219BFFFAIPS-2 (OPACR6)uSDHC316 KB
0219400002197FFFAIPS-2 (OPACR5)uSDHC216 KB
0219000002193FFFAIPS-2 (OPACR4)uSDHC116 KB
0218C0000218FFFFAIPS-2 (OPACR3)MLB15016 KB
021880000218BFFFAIPS-2 (OPACR2)ENET16 KB
0218400002187FFFAIPS-2 (OPACR1)USBOH316 KB
0218000002183FFFAIPS-2 (OPACR0)Reserved16 KB
0217C0000217FFFFAIPS-2AIPS216 KB
021610000217BFFFAIPS-2 Global Module Enable (OPACR33)Reserved108 KB
0214000002160FFFARM_MPCORE_DAP132 KB
021100000213FFFFAIPS-2 Global Module Enable (OPACR32)Reserved192 KB
021000000210FFFFCAAM64 KB

   


 

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ffm
Contributor III

Hi all,

I got a response to my SR from Freescale, which more or less gave the answers. So I post here a version created by myself and as suggested to Freescale of those parts (Tables 2-2 and 2-3 in RM):

   

Start AddressEnd AddressRegionNIC PortSize
020FC000020FFFFFAIPS-1 (OPACR31)Reserved16 KB
020F8000020FBFFFAIPS-1 (OPACR30)Reserved16 KB
020F4000020F7FFFAIPS-1 (OPACR29)Reserved16 KB
020F0000020F3FFFAIPS-1 (OPACR28)Reserved16 KB
020EC000020EFFFFAIPS-1 (OPACR27)SDMA16 KB
020E8000020EBFFFAIPS-1 (OPACR26)DCIC216 KB
020E4000020E7FFFAIPS-1 (OPACR25)DCIC116 KB
020E0000020E3FFFAIPS-1 (OPACR24)IOMUXC16 KB
020DC2B0020DFFFFAIPS-1 (OPACR23)Reserved15696 B
020DC2A0020DC2AFPGC_CPU16 B
020DC270020DC29FReserved48 B
020DC260020DC26FPGC_GPU16 B
020DC1C4020DC25FReserved156 B
020DC180020DC1C3DVFS68 B
020DC028020DC17FReserved344 B
020DC000020DC027GPC40 B
020D8000020DBFFFAIPS-1 (OPACR22)SRC16 KB
020D4000020D7FFFAIPS-1 (OPACR21)EPIT216 KB
020D0000020D3FFFAIPS-1 (OPACR20)EPIT116 KB
020CC000020CFFFFAIPS-1 (OPACR19)SNVS_HP16 KB
020CB000020CBFFFAIPS-1 (OPACR18)Reserved4 KB
020CA000020CAFFFUSBPHY24 KB
020C9000020C9FFFUSBPHY14 KB
020C8000020C8FFFCCM_ANALOG4 KB
020C4000020C7FFFAIPS-1 (OPACR17)CCM_DIGITAL16 KB
020C0000020C3FFFAIPS-1 (OPACR16)WDOG216 KB
020BC000020BFFFFAIPS-1 (OPACR15)WDOG116 KB
020B8000020BBFFFAIPS-1 (OPACR14)KPP16 KB
020B4000020B7FFFAIPS-1 (OPACR13)GPIO716 KB
020B0000020B3FFFAIPS-1 (OPACR12)GPIO616 KB
020AC000020AFFFFAIPS-1 (OPACR11)GPIO516 KB
020A8000020ABFFFAIPS-1 (OPACR10)GPIO416 KB
020A4000020A7FFFAIPS-1 (OPACR9)GPIO316 KB
020A0000020A3FFFAIPS-1 (OPACR8)GPIO216 KB
0209C0000209FFFFAIPS-1 (OPACR7)GPIO116 KB
020980000209BFFFAIPS-1 (OPACR6)GPT16 KB
0209400002097FFFAIPS-1 (OPACR5)CAN216 KB
0209000002093FFFAIPS-1 (OPACR4)CAN116 KB
0208C0000208FFFFAIPS-1 (OPACR3)PWM416 KB
020880000208BFFFAIPS-1 (OPACR2)PWM316 KB
0208400002087FFFAIPS-1 (OPACR1)PWM216 KB
0208000002083FFFAIPS-1 (OPACR0)PWM116 KB
0207C0000207FFFFAIPS-1AIPS116 KB
020400000207BFFFAIPS-2 Global Module Enable (OPACR33)VPU240 KB
0203C0000203FFFFAIPS-2 Global Module Enable (OPACR32)SPBA16 KB
020380000203BFFFReserved16 KB
0203400002037FFFASRC16 KB
0203000002033FFFSSI316 KB
0202C0000202FFFFSSI216 KB
020280000202BFFFSSI116 KB
0202400002027FFFESAI16 KB
0202000002023FFFUART116 KB
0201C0000201FFFFReserved16 KB
020180000201BFFFeCSPI516 KB
0201400002017FFFeCSPI416 KB
0201000002013FFFeCSPI316 KB
0200C0000200FFFFeCSPI216 KB
020080000200BFFFeCSPI116 KB
0200400002007FFFSPDIF16 KB
0200000002003FFFReserved16 KB


   

Start AddressEnd AddressRegionNIC PortSize
021FC000021FFFFFAIPS-2 (OPACR31)Reserved16 KB
021F8000021FBFFFAIPS-2 (OPACR30)Reserved16 KB
021F4000021F7FFFAIPS-2 (OPACR29)UART516 KB
021F0000021F3FFFAIPS-2 (OPACR28)UART416 KB
021EC000021EFFFFAIPS-2 (OPACR27)UART316 KB
021E8000021EBFFFAIPS-2 (OPACR26)UART216 KB
021E4000021E7FFFAIPS-2 (OPACR25)VDOA16 KB
021E0000021E3FFFAIPS-2 (OPACR24)MIPI_DSI16 KB
021DC000021DFFFFAIPS-2 (OPACR23)MIPI_CSI16 KB
021D8000021DBFFFAIPS-2 (OPACR22)AUDMUX16 KB
021D4000021D7FFFAIPS-2 (OPACR21)TZASC216 KB
021D0000021D3FFFAIPS-2 (OPACR20)TZASC116 KB
021CC000021CFFFFAIPS-2 (OPACR19)Reserved16 KB
021C8000021CBFFFAIPS-2 (OPACR18)Reserved16 KB
021C4000021C7FFFAIPS-2 (OPACR17)Reserved16 KB
021C0000021C3FFFAIPS-2 (OPACR16)CSU16 KB
021BC000021BFFFFAIPS-2 (OPACR15)OCOTP_CTRL16 KB
021B8000021BBFFFAIPS-2 (OPACR14)EIM16 KB
021B4000021B7FFFAIPS-2 (OPACR13)MMDC116 KB
021B0000021B3FFFAIPS-2 (OPACR12)MMDC016 KB
021AC000021AFFFFAIPS-2 (OPACR11)ROMCP16 KB
021A8000021ABFFFAIPS-2 (OPACR10)I2C316 KB
021A4000021A7FFFAIPS-2 (OPACR9)I2C216 KB
021A0000021A3FFFAIPS-2 (OPACR8)I2C116 KB
0219C0000219FFFFAIPS-2 (OPACR7)uSDHC416 KB
021980000219BFFFAIPS-2 (OPACR6)uSDHC316 KB
0219400002197FFFAIPS-2 (OPACR5)uSDHC216 KB
0219000002193FFFAIPS-2 (OPACR4)uSDHC116 KB
0218C0000218FFFFAIPS-2 (OPACR3)MLB15016 KB
021880000218BFFFAIPS-2 (OPACR2)ENET16 KB
0218400002187FFFAIPS-2 (OPACR1)USBOH316 KB
0218000002183FFFAIPS-2 (OPACR0)Reserved16 KB
0217C0000217FFFFAIPS-2AIPS216 KB
021610000217BFFFAIPS-2 Global Module Enable (OPACR33)Reserved108 KB
0214000002160FFFARM_MPCORE_DAP132 KB
021100000213FFFFAIPS-2 Global Module Enable (OPACR32)Reserved192 KB
021000000210FFFFCAAM64 KB

   


 

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Rob_iMX6
Contributor II

Hi Frank

I've just stumbled upon the same question...

Did you get the mappings from Fresscale? If so, could you please post them here?

Thanks in advance and best regards,

-Urs

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ffm
Contributor III

Hi Rob,

I did not yet get an answer from Frescale support. Otherwise I would of course have posted the mapping here to be available to the comunity. Anyway I started manually testing, which of the peripherals shows a reaction on changing the flags. It seamsthat the order of the peripherals (16K-blocks) in the memory map in chapter 2 matches the order of the OPACR registers. Currently I checked only the following peripherals:
PWM1   -> AIPSTZ1_OPACR.OPAC0
PWM2   -> AIPSTZ1_OPACR.OPAC1
GPIO1  -> AIPSTZ1_OPACR.OPAC7
GPIO2  -> AIPSTZ1_OPACR1.OPAC8
GPIO7  -> AIPSTZ1_OPACR1.OPAC13
CCM    -> AIPSTZ1_OPACR2.OPAC17
IOMUXC -> AIPSTZ1_OPACR3.OPAC24

I further guess that AIPSTZ1_OPACR3.OPAC32 and AIPSTZ1_OPACR3.OPAC33 are the so called global module enables and map to all or at least multiple of those peripherals in the memory map in chapter 2, which are stated to be AIPS-1 Global Module Enable. The question here, which I can't answer yet, is: Do all those peripherals map to AIPSTZ1_OPACR3.OPAC32 or is there a split between AIPSTZ1_OPACR3.OPAC32 and AIPSTZ1_OPACR3.OPAC33? If there is no split, which peripheral(s) map to AIPSTZ1_OPACR3.OPAC33?

Another point is, that it seams that the AIPS itself, which is also a peripheral (16K-block), has no access control.

And one more point is, that the iMX6 implements another peripheral, the so called central security unit (CSU) which has very similar purpose and features. Some of the peripherals are access controlled by both, one AIPS and the CSU, others are access controlled by the CSU only. I'm not yet sure whether peripherals exist which are access controlled only by the AIPS and I even do not know the priority/dependency of the access permission between those two control facilities (AIPS and CSU).

Regards, Frank

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Rob_iMX6
Contributor II

Hi Frank

Thanks a lot for this insight, very interesting! For now I will leave accesses open, though... and come back to this mapping question later, once everything works.

Best regards,

-Urs or Rob, my middle name, as the first name is pretty unkown... :-)

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igorpadykov
NXP Employee
NXP Employee

Hi Frank

suggest to create SR to tech support, this table with peripherals

will be provided. Regarding " addresses for AIPS1 and AIPS2 given in the

register map in chapter 13 are wrong" - RM Chapter description is just generic description,

specific addresses one needs to look at chapter 2.

Best regards

chip

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ffm
Contributor III

Hi chipexpert,

thanks for your answer. I will create ans SR.

Regarding the address issue: Don't you assent that in a generic desription it would be better to give just the register offsets rather than absoulute addresses?

Regards, Frank

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igorpadykov
NXP Employee
NXP Employee

Hi Frank

I think yes

Best regards

chip

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