Does J14 or N3 of imx.rt 1062 can be configured as GPIO when using XIP with SPI NOR FLASH

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Does J14 or N3 of imx.rt 1062 can be configured as GPIO when using XIP with SPI NOR FLASH

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Contributor I

ROM Bootloader Peripheral PinMux set these two pads as:

Port ( IO function) PAD Mode

J14 :

FLEXSPI_A_SS0_B GPIO_AD_B1_15

ALT0

N3:

FLEXSPI_A_DQS GPIO_SD_B1_05 ALT1
GPIO_AD_B1_09 ALT0


We would like set these pin as GPIO in pint_mux.c such that:

  IOMUXC_SetPinMux(
      IOMUXC_GPIO_AD_B1_15_GPIO1_IO31,          /* GPIO_AD_B1_15 is configured as GPIO1_IO31 */
      0U);

  IOMUXC_SetPinMux(
      IOMUXC_GPIO_SD_B1_05_GPIO3_IO05,        /* GPIO_SD_B1_05 is configured as GPIO3_IO05 */
      0U);        

Either IOMUXC_SetPinMux will result in a system reset when XIP in flex nor flash tested on MIMXRT1060-EVK board.

So, Does J14 or N3 of imx.rt 1062 can be configured as GPIO when using XIP with SPI NOR FLASH.

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NXP TechSupport
NXP TechSupport

Hi frank zheng

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
1) Does J14 or N3 of imx.rt 1062 can be configured as GPIO when using XIP with SPI NOR FLASH?
-- Yes, it's feasible.

Have a great day,
TIC

 

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Contributor I

Hi Jeremy,
     When try to   config either pin as GPIO,result in a system reset.
     Could please have a test on you side.

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NXP TechSupport
NXP TechSupport

Hi frank zheng

Thanks for your reply.
Whether you can introduce the testing process you did and result in details, it can help me to figure the issue out.
Have a great day,
TIC

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Contributor I


The iled_blinky example of demo_apps in SDK is cloned, and the led_blinky flexspi_nor_debug is choosed,

After add this

IOMUXC_SetPinMux(
      IOMUXC_GPIO_AD_B1_15_GPIO1_IO31,          /* GPIO_AD_B1_15 is configured as GPIO1_IO31 */
      0U);

  or that

  IOMUXC_SetPinMux(
      IOMUXC_GPIO_SD_B1_05_GPIO3_IO05,        /* GPIO_SD_B1_05 is configured as GPIO3_IO05 */
      0U);      

 in the tail of function void BOARD_InitPins(void) ,then build and download the image into EVK board,  

the problem is occurred.

Pls have a look at this issue,thank you.

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NXP TechSupport
NXP TechSupport

Hi frank zheng

Thanks for your reply.
I've added the below code in the BOARD_InitPins(void), the demo still works well, so I was wondering if you can describe what kink of problem you encounter.

  IOMUXC_SetPinMux(
        IOMUXC_GPIO_AD_B1_15_GPIO1_IO31,          /* GPIO_AD_B1_15 is configured as GPIO1_IO31 */
        0U);


  IOMUXC_SetPinConfig(
   IOMUXC_GPIO_AD_B1_15_GPIO1_IO31,        /* GPIO_AD_B1_15 PAD functional properties : */
      0x10B0U);                               /* Slew Rate Field: Slow Slew Rate
                                                 Drive Strength Field: R0/6
                                                 Speed Field: medium(100MHz)
                                                 Open Drain Enable Field: Open Drain Disabled
                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
                                                 Pull / Keep Select Field: Keeper
                                                 Pull Up / Down Config. Field: 100K Ohm Pull Down
                                                 Hyst. Enable Field: Hysteresis Disabled */

Have a great day,
TIC

 

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Contributor I

Check this one more times,

IOMUXC_SetPinMux(
        IOMUXC_GPIO_AD_B1_15_GPIO1_IO31,          /* GPIO_AD_B1_15 is configured as GPIO1_IO31 */
        0U);

  IOMUXC_SetPinConfig(
       IOMUXC_GPIO_AD_B1_15_GPIO1_IO31,        /* GPIO_AD_B1_15 PAD functional properties : */
      0x10B0U);                               /* Slew Rate Field: Slow Slew Rate
                                                 Drive Strength Field: R0/6
                                                 Speed Field: medium(100MHz)
                                                 Open Drain Enable Field: Open Drain Disabled
                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
                                                 Pull / Keep Select Field: Keeper
                                                 Pull Up / Down Config. Field: 100K Ohm Pull Down
                                                 Hyst. Enable Field: Hysteresis Disabled */
 IOMUXC_SetPinMux(
      IOMUXC_GPIO_SD_B1_05_GPIO3_IO05,        /* GPIO_SD_B1_05 is configured as GPIO3_IO05 */
      0U);     
  IOMUXC_SetPinConfig(
       IOMUXC_GPIO_SD_B1_05_GPIO3_IO05,        /* GPIO_SD_B1_05 PAD functional properties : */
      0x10B0U);                               /* Slew Rate Field: Slow Slew Rate
                                                 Drive Strength Field: R0/6
                                                 Speed Field: medium(100MHz)
                                                 Open Drain Enable Field: Open Drain Disabled
                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
                                                 Pull / Keep Select Field: Keeper
                                                 Pull Up / Down Config. Field: 100K Ohm Pull Down
                                                 Hyst. Enable Field: Hysteresis Disabled */
is added,and set a breakpoint at Reset_Handler in startup_MIMXRT1062.s , got a reset.reset.png 
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NXP TechSupport
NXP TechSupport

Hi frank zheng

Thanks for your reply.

For QSPI Flash as XIP function, to achieve the highest performance it needs to left FLEXSPI_A_DQS(GPIO_SD_B1_05)pin floating and configure sample clock source as 01-loopback from DQS pad mode to archive max 133MHz Flexspi_clk.
I think it's the root cause of the issue.

Hope it helps.

Have a great day,
TIC

 

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