Different rgmii timing budgets on imx6 processors

[diarmuidcollins]

I'm developing an FPGA that interfaces to an imx6Dual processor. Previously I have implemented another design connecting to the imx6DualLite processor

I've noticed that the rgmii timing budgets for the two devices are different. I thought this was unusual as the two designs are so close. Specifically the "Data to clock output skew at transmitter"

Can you confirm that the numbers in the datasheet are correct?

imx6Dual - Table 54

https://www.nxp.com/docs/en/data-sheet/IMX6SDLAEC.pdf

imx6DualLite - Table 60

https://www.nxp.com/docs/en/data-sheet/IMX6SDLAEC.pdf

[diarmuidcollins]

@nxf63675  HI Israel, Have you had any thoughts about my second question here?  https://community.nxp.com/t5/i-MX-Processors/Different-rgmii-timing-budgets-on-imx6-processors/m-p/1... 

[diarmuidcollins]

@nxf63675 Thanks Israel for the response.

I understand that in both cases the timing window respects the rgmii requirement.

What's confusing me is that the differences in the TskewT reported in the datasheet suggests that the two devices have significantly different timing in silicon. However I was expecting that as both devices are so functionally close and from the same family, that they would have had the same interface timing. Can you confirm that these two devices have different silicon and as a result different interface timing?

As I'm connecting to an FPGA, I can constrain the interface timing in the FPGA and manage the clock and data skews inside the device, and not in the PCB traces. However that's why these absolute numbers are critical to me.

[nxf63675]

Hi @diarmuidcollins,

This info cannot be shared in the community, please submit a ticket and someone will contact you, sorry for the problems this may cause you.

https://www.nxp.com/support/support:SUPPORTHOME

Regards,

Israel.

[nxf63675]

Hi @diarmuidcollins,

The info on the datasheet is correct, The RGMII v1.3 specification defines the TskewT range of -500 to 500 ps. Table 62 of the IMX6DQAEC Data Sheet document specifies the TskewT range of -100 to 900 ps. So, the total skew amount of 1ns is equal for both cases. Then, providing the specified TskewR range of 1ns to 2.6ns is the matter of PCB design. There is a footnote to Table 62, saying that "PC board design will require clocks to be routed such that an additional delay of greater than 1.2 ns and less than 1.7 ns will be added to the associated clock signal". Meeting this condition provides the specified TskewR range of 1ns to 2.6ns.

If there is something more I can do for you please let me know.

Regards,

Israel.