Device tree of i.MX8m Plus, CS of SPI

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Device tree of i.MX8m Plus, CS of SPI

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acremonini
Contributor II

Hello,

I'm working on the device tree of a board derived from i.mx8m plus EVK.

I see in the device tree  (file imx8mp-evk.dts) that the CS pin is set as GPIO (I suppose is the way the driver uses it) but i can't understand the pad setting:

&iomuxc {

...

pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82
>;
};

pinctrl_ecspi2_cs: ecspi2cs {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000
>;
};

...

I understand that the last number is mainly the setting of pad register, but the only bits with a meaning in that register are the ones from 0 to 8, so I can't imagine the use of the 1 in the 18th bit. The only exception I know is the SION bit, like for I2C pins, that adds a 1 in position 30 as explained in fsl,imx-pinctrl.txt

Bits used for CONFIG:
NO_PAD_CTL(1 << 31): indicate this pin does not need config.

SION(1 << 30): Software Input On Field.
Force the selected mux mode input path no matter of MUX_MODE functionality.
By default the input path is determined by functionality of the selected
mux mode (regular).

Other bits are used for PAD setting.

Could someone explain me that setting of chip select pad register?

Thanks,

Antonio

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1 Reply

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Dhruvit
NXP TechSupport
NXP TechSupport

Hi @acremonini,

I hope you are doing well
 
Yes, you are correct. Modification is valid on bits 0 to 8. Other bits are reserved. It seems that there is a typing error.
The reserved bits are by default set as zero. If we try to modify those bits, it will be ignored.
 
Thanks & Regards,
Dhruvit Vasavada
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