Device Tree eDMA3 "i.MX 8QuadXPlus"

[xaviersoulie]

Hi all,

I want to define the eDMA3 resource on an "i.MX 8QuadXPlus" processor via the device tree.
After searching online, I haven't found a device tree for this processor that includes this definition.
Could you please tell me how I can create this resource?
I can't find the methodology for providing an IRQ number for the GIC_SPI parameter.
Is there a guide for creating this?
Thank you in advance for your help.

Best Regards

Xavier

[pengyong_zhang]

Hi @xaviersoulie 

Sorry to reply late, what is your BSP code version?

B.R

[xaviersoulie]

Hi,
We do not use Linux in our project. We use a different RTOS.
Thank you

[Zhiming_Liu]

Hi @xaviersoulie 

You can find definitions in linux dts: arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi

	edma3: dma-controller@5a9f0000 {
		compatible = "fsl,imx8qm-edma";
		reg = <0x5a9f0000 0x90000>;
		#dma-cells = <3>;
		dma-channels = <8>;
		interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&pd IMX_SC_R_DMA_3_CH0>,
				<&pd IMX_SC_R_DMA_3_CH1>,
				<&pd IMX_SC_R_DMA_3_CH2>,
				<&pd IMX_SC_R_DMA_3_CH3>,
				<&pd IMX_SC_R_DMA_3_CH4>,
				<&pd IMX_SC_R_DMA_3_CH5>,
				<&pd IMX_SC_R_DMA_3_CH6>,
				<&pd IMX_SC_R_DMA_3_CH7>;
	};

Best Regards,
Zhiming

[xaviersoulie]

Hello Zhiming
Thank you very much for this data.
I have a related question: in the compatible field = "fsl,imx8qm-edma", it indicates imx8qm. Could you tell me why it doesn't say "imx8qxp"? Is there a difference between an imx8xqm and an imx8qxp processor for this node in the device tree?
Furthermore, I want to expand this definition to be able to use all 16 channels of the EDMA3. How do I complete this definition?
I want to use the adc0 device with channel 8 of the EDMA3. Are there also guidelines for defining these nodes (EDMA3 channel 8 and adc0)?
Thank you in advance for your feedback and advice.

[Zhiming_Liu]

Hi,

The i.MX8QM and i.MX8QXP share lots of peripherals. The device tree inclusion relationship is:

imx8qxp.dtsi
  -->imx8-ss-adma.dtsi
    -->imx8-ss-dma.dtsi

If you are not using Linux, you should refer the imx8-ss-dma.dtsi and reference manual to define your edma3 node. For the 8 channel adc, you can refer linux driver:drivers/iio/adc/imx8qxp-adc.c, this driver is using 8 channels

Best Regards,
Zhiming