Customer is considering to develop the system using i.MX6DualLite.
Customer wants to generate the interrupt to CPU core with VSYNC.
I think that i.MX6DL has two camera I/F, Parallel interface and MIPI CSI-2.
1. Parallel interface
I think that it is able to connect the VSYNC signal with GPIO when it use the Parallel interface for the camera I/F.
Is my understanding correct?
2. MIPI CSI-2
How is it able to detect the VSYNC and notice it to the CPU core when it use the MIPI for camera I/F?
Is there any register to detect the VSYNC when it use the MIPI for the camera I/F?
Q1) for connecting, pls refer to the CSI0_VSYNC in the Table 4-1. Pin Assignments of Reference Manual
Q2)For CSI non-gated mode, the IPU will only capture the low to high modification on VSYNC, so if your sensor can generate such trigger for each frame, it is OK to keep the VSYNC in high for whole frame.
And for non-gated clock mode, data enable was also needed, and pixel clock should be ticking only when data is valid.
VIDIOC_STREAMOFF was supported in mxc_v4l2_capture.c of freescale kernel.