Hi community,
We have a question about i.MX6SDL HDMI.
Please see chapter 34.5.314 ~ 34.5.321 in IMX6SDLRM (Rev.1).
There are no descriptions for these registers.
Would you let me know the detail of these registers?
Best Regards,
Satoshi Shimoda
Solved! Go to Solution.
The following *CNT registers must be set before any I2C bus transaction
can take place to ensure proper I/O timing. The *CNT registers are:
- *_I2CM_SS_SCL_HCNT
- *_I2CM_SS_SCL_LCNT
- *_I2CM_FS_SCL_HCNT
- *_I2CM_FS_SCL_LCNT
The following abbreviation is used for I2C SCL clock settings:
• SS: Standard Speed
• FS: Fast Speed
• HCNT: SCL High Level counter
• LCNT: SCL Low Level counter
Have a great day,
Yuri.
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The following *CNT registers must be set before any I2C bus transaction
can take place to ensure proper I/O timing. The *CNT registers are:
- *_I2CM_SS_SCL_HCNT
- *_I2CM_SS_SCL_LCNT
- *_I2CM_FS_SCL_HCNT
- *_I2CM_FS_SCL_LCNT
The following abbreviation is used for I2C SCL clock settings:
• SS: Standard Speed
• FS: Fast Speed
• HCNT: SCL High Level counter
• LCNT: SCL Low Level counter
Have a great day,
Yuri.
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
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