Deinterlace ISL79987 on IMX8QXP

[tugayilbay]

Hi,

I am using Linux v5.4.42 with Digi's yocto embedded v3.0r1. I am trying to merge the changes provided in the link below to the current kernel. I want to use weaving deinterlace without blending support since my im8qxp chip version is B0.

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/ISL79987-and-adv7180-de-interlace-driver...

After I applied the patches, I tried to show the incoming frames. Sometimes I see a green frames or sometimes nothing at all when I executed the application. For each execution one of these two occurs. I also realized that mipi csi2 csr registers are all 0. So I suspected that something I did broke something and then reverted all the changes. However, these registers' values did not change despite I can see the incoming odd/even frames.

Could you guide me where I did wrong?

I attached the changes I made to this post:

Here is my register dump:

[ 46.843704] input fmt YUV4
[ 46.846474] output fmt YUYV
[ 46.849306] mxc_isi_channel_set_scaling: no scale
[ 46.855129] dump_isi_regs ISI CHNLC register dump, isi0
[ 46.860426] dump_isi_regs CHNL_CTRL[0x00]: e0ff0002
[ 46.866286] dump_isi_regs CHNL_IMG_CTRL[0x04]: 20002001
[ 46.872169] dump_isi_regs CHNL_OUT_BUF_CTRL[0x08]: c092
[ 46.877685] dump_isi_regs CHNL_IMG_CFG[0x0c]: f002d0
[ 46.883757] dump_isi_regs CHNL_IER[0x10]: 3dff0000
[ 46.889627] dump_isi_regs CHNL_STS[0x14]: 200
[ 46.895078] dump_isi_regs CHNL_SCALE_FACTOR[0x18]: 10001000
[ 46.900944] dump_isi_regs CHNL_SCALE_OFFSET[0x1c]: 00
[ 46.906310] dump_isi_regs CHNL_CROP_ULC[0x20]: 00
[ 46.911654] dump_isi_regs CHNL_CROP_LRC[0x24]: 00
[ 46.916990] dump_isi_regs CHNL_CSC_COEFF0[0x28]: 00
[ 46.922323] dump_isi_regs CHNL_CSC_COEFF1[0x2c]: 00
[ 46.927688] dump_isi_regs CHNL_CSC_COEFF2[0x30]: 00
[ 46.933036] dump_isi_regs CHNL_CSC_COEFF3[0x34]: 00
[ 46.938392] dump_isi_regs CHNL_CSC_COEFF4[0x38]: 00
[ 46.943732] dump_isi_regs CHNL_CSC_COEFF5[0x3c]: 00
[ 46.949070] dump_isi_regs CHNL_ROI_0_ALPHA[0x40]: 00
[ 46.954404] dump_isi_regs CHNL_ROI_0_ULC[0x44]: 00
[ 46.959763] dump_isi_regs CHNL_ROI_0_LRC[0x48]: 00
[ 46.965111] dump_isi_regs CHNL_ROI_1_ALPHA[0x4c]: 00
[ 46.970464] dump_isi_regs CHNL_ROI_1_ULC[0x50]: 00
[ 46.975808] dump_isi_regs CHNL_ROI_1_LRC[0x54]: 00
[ 46.981145] dump_isi_regs CHNL_ROI_2_ALPHA[0x58]: 00
[ 46.986493] dump_isi_regs CHNL_ROI_2_ULC[0x5c]: 00
[ 46.991853] dump_isi_regs CHNL_ROI_2_LRC[0x60]: 00
[ 46.997202] dump_isi_regs CHNL_ROI_3_ALPHA[0x64]: 00
[ 47.002561] dump_isi_regs CHNL_ROI_3_ULC[0x68]: 00
[ 47.007901] dump_isi_regs CHNL_ROI_3_LRC[0x6c]: 00
[ 47.013237] dump_isi_regs CHNL_OUT_BUF1_ADDR_Y[0x70]: bce00000
[ 47.019091] dump_isi_regs CHNL_OUT_BUF1_ADDR_U[0x74]: 00
[ 47.024447] dump_isi_regs CHNL_OUT_BUF1_ADDR_V[0x78]: 00
[ 47.029797] dump_isi_regs CHNL_OUT_BUF_PITCH[0x7c]: 5a0
[ 47.035239] dump_isi_regs CHNL_IN_BUF_ADDR[0x80]: 00
[ 47.040582] dump_isi_regs CHNL_IN_BUF_PITCH[0x84]: 00
[ 47.045952] dump_isi_regs CHNL_MEM_RD_CTRL[0x88]: 00
[ 47.051299] dump_isi_regs CHNL_OUT_BUF2_ADDR_Y[0x8c]: bca00000
[ 47.057161] dump_isi_regs CHNL_OUT_BUF2_ADDR_U[0x90]: 00
[ 47.062495] dump_isi_regs CHNL_OUT_BUF2_ADDR_V[0x94]: 00
[ 47.067849] dump_isi_regs CHNL_SCL_IMG_CFG[0x98]: f002d0
[ 47.408909] mxc_mipi_csi2_reg_dump MIPI CSI2 CSR and HC register dump, mipi csi0
[ 47.416356] mxc_mipi_csi2_reg_dump MIPI CSI2 HC num of lanes[0x100]: 0x001
[ 47.423261] mxc_mipi_csi2_reg_dump MIPI CSI2 HC dis lanes[0x104]: 0x00c
[ 47.429902] mxc_mipi_csi2_reg_dump MIPI CSI2 HC BIT ERR[0x108]: 0x000
[ 47.436371] mxc_mipi_csi2_reg_dump MIPI CSI2 HC IRQ STATUS[0x10c]: 0x008
[ 47.443102] mxc_mipi_csi2_reg_dump MIPI CSI2 HC IRQ MASK[0x110]: 0x1ff
[ 47.449652] mxc_mipi_csi2_reg_dump MIPI CSI2 HC ULPS STATUS[0x114]: 0x000
[ 47.456466] mxc_mipi_csi2_reg_dump MIPI CSI2 HC DPHY ErrSotHS[0x118]: 0x000
[ 47.463467] mxc_mipi_csi2_reg_dump MIPI CSI2 HC DPHY ErrSotSync[0x11c]: 0x000
[ 47.470634] mxc_mipi_csi2_reg_dump MIPI CSI2 HC DPHY ErrEsc[0x120]: 0x000
[ 47.477444] mxc_mipi_csi2_reg_dump MIPI CSI2 HC DPHY ErrSyncEsc[0x124]: 0x000
[ 47.484611] mxc_mipi_csi2_reg_dump MIPI CSI2 HC DPHY ErrControl[0x128]: 0x000
[ 47.491775] mxc_mipi_csi2_reg_dump MIPI CSI2 HC DISABLE_PAYLOAD[0x12c]: 0x000
[ 47.498964] mxc_mipi_csi2_reg_dump MIPI CSI2 HC DISABLE_PAYLOAD[0x130]: 0x000
[ 47.506133] mxc_mipi_csi2_reg_dump MIPI CSI2 HC IGNORE_VC[0x180]: 0x000
[ 47.512802] mxc_mipi_csi2_reg_dump MIPI CSI2 HC VID_VC[0x184]: 0x000
[ 47.519271] mxc_mipi_csi2_reg_dump MIPI CSI2 HC FIFO_SEND_LEVEL[0x188]: 0x000
[ 47.526435] mxc_mipi_csi2_reg_dump MIPI CSI2 HC VID_VSYNC[0x18c]: 0x000
[ 47.533067] mxc_mipi_csi2_reg_dump MIPI CSI2 HC VID_SYNC_FP[0x190]: 0x000
[ 47.539882] mxc_mipi_csi2_reg_dump MIPI CSI2 HC VID_HSYNC[0x194]: 0x000
[ 47.546516] mxc_mipi_csi2_reg_dump MIPI CSI2 HC VID_HSYNC_BP[0x198]: 0x000
[ 47.553418] mxc_mipi_csi2_reg_dump MIPI CSI2 CSR PLM_CTRL[0x000]: 0x000
[ 47.560072] mxc_mipi_csi2_reg_dump MIPI CSI2 CSR PHY_CTRL[0x004]: 0x000
[ 47.566716] mxc_mipi_csi2_reg_dump MIPI CSI2 CSR PHY_Status[0x008]: 0x000
[ 47.573529] mxc_mipi_csi2_reg_dump MIPI CSI2 CSR PHY_Test_Status[0x010]: 0x000
[ 47.580773] mxc_mipi_csi2_reg_dump MIPI CSI2 CSR PHY_Test_Status[0x014]: 0x000
[ 47.588022] mxc_mipi_csi2_reg_dump MIPI CSI2 CSR PHY_Test_Status[0x018]: 0x000
[ 47.595287] mxc_mipi_csi2_reg_dump MIPI CSI2 CSR PHY_Test_Status[0x01c]: 0x000
[ 47.602545] mxc_mipi_csi2_reg_dump MIPI CSI2 CSR PHY_Test_Status[0x020]: 0x000
[ 47.609792] mxc_mipi_csi2_reg_dump MIPI CSI2 CSR VC Interlaced[0x030]: 0x000
[ 47.616861] mxc_mipi_csi2_reg_dump MIPI CSI2 CSR Data Type Dis[0x038]: 0x000
[ 47.623934] mxc_mipi_csi2_reg_dump MIPI CSI2 CSR 420 1st type[0x040]: 0x000
[ 47.630939] mxc_mipi_csi2_reg_dump MIPI CSI2 CSR Ctr_Ck_Rst_Ctr[0x044]: 0x000
[ 47.638111] mxc_mipi_csi2_reg_dump MIPI CSI2 CSR Stream Fencing[0x048]: 0x000
[ 47.645269] mxc_mipi_csi2_reg_dump MIPI CSI2 CSR Stream Fencing[0x04c]: 0x000

[jimmychan]

According to the document "https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/ISL79987-and-adv7180-de-interlace-driver...  ISL79987 is the 4 virtual channel TVin chip which can input 4 CVBS cameras to iMX8QXP with MIPI CSI2 inteface, it can only work with iMX8QXP C0 chips. The iMX8QXP B0 chips have MIPI CSI2 virtual channel errata.