Debugging imprecise external aborts on i.MX6

[niranjandighe]

Hello All,

I am trying to debug some spurious imprecise external aborts (0x1406) (not really spurious, whenever they occur they occur at around 45 seconds from start).

I am trying to dump some information about the system state when the fault occured. I need to know -

Question 1

if i.MX6 implements the auxiliary status register

as described by ARM manual -

Accessing the ADFSR and AIFSR

To access the ADFSR or AIFSR you read or write the CP15 registers with <opc1> set to 0, <CRn> set to c5,

<CRm> set to c1, and <opc2> set to:

• 0 for the ADFSR

• 1 for the AIFSR.

For example:

MRC p15,0,<Rt>,c5,c1,0 ; Read CP15 Auxiliary Data Fault Status Register

MCR p15,0,<Rt>,c5,c1,0 ; Write CP15 Auxiliary Data Fault Status Register

MRC p15,0,<Rt>,c5,c1,1 ; Read CP15 Auxiliary Instruction Fault Status Register

MCR p15,0,<Rt>,c5,c1,1 ; Write CP15 Auxiliary Instruction Fault Status Register

I also need to know the details of bit fields etc so that I can get some information about the faults.

Question 2

The ARM manual describes the DFSR encoding as - Bit fields [11,10,3:0]. 11th bit -> read/write

However the DFSR value - 0x1406 has 12th bit set. Which according to manual is undefined. I need to know what is the implementation in i.MX6.

Thanks,

Niranjan Dighe

[igorpadykov]

Hi Niranjan

1. yes i.MX6 implements the auxiliary status register

2. implementation in i.MX6 does not change from arm docs descriptions.

Best regards

igor

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[niranjandighe]

ARM documentation does not specify the detailed bit fields and it says that

it is up to the chip vendor to decide and design, what goes into the

register. Typical implementation would include details about source of

external abort. But this info is not captured in i.MX6 TRM.

[igorpadykov]

Hi Niranjan

could you provide arm document full name and link which tells:

"it says that it is up to the chip vendor to decide and design, what goes into the

register."

Best regards

igor

[niranjandighe]

I am referring the ARM v7 Architecture Reference Manual, page number -

1327, setction B3.9.8.

Please find the snapshot below -

Thanks,

Niranjan Dighe

On Tue, May 19, 2015 at 2:47 PM, igorpadykov <admin@community.freescale.com>

[igorpadykov]

Hi Niranjan

attached part of document says:

"contents.. of registers is IMPLEMENTATION defined"

that is content may depend on processor architecture: Cortex A5,A9

e.t.c. nothing said about chip vendor.

Best regards

igor