Debugging IMX6Q IPU via JTAG

[craig1]

Does anyone have experience accessing the IPU registers directly using a JTAG debug tool?  I need to verify that the settings being passed to the CSI configuration registers are correct.

The addresses in the RM aren't making sense to me.  Using a Lauterbach debugger I expect to be able to access the IPU registers directly when the processor is taken out of reset before enabling the MMU (e.g., stopped in u-boot).  Bus Errors occur when using the addresses in the RM Memory map  and also when using values contained in plat_mxc/include/mach/mx6.h.  It should be noted that the memory maps in the RM appear to have a discontinuity between sections 2 & 39.

It appears the addresses in the perimx6.per file provided by FSL point to the middle of DDR (0x20400000), so they are useless.

[craig1 · Accepted solution]

To follow-up on this it appears that section 2 of the RM states addresses as absolute but is really relative and section 39 alludes to addresses being relative but they actually have the IPUV3H_REG_BASE offset already added in.

The IPU appears to be held in a reset or non-clocked state when in serial downloader mode so registers cant be viewed until it is initialized.  This can occur by booting into linux then running a script to shut down the MMU and allow direct access to the addresses defined in section 39 or by loading the MMU tables and allowing the trace32 tool to do the virtual address translation.

[craig1]

And to close out the issue,

It turned out we had enabled the CSI0_DATA_EN in our iMX6Q pin-muxing.  This was ignored by CCIR devices but had a negative effect on gated devices.  Not sure the correct way to configure data_en with hsync and vsync as the RM would imply this signal is not used (Figure 37-17. gated mode).  Inverting its polarity resulted in the eba callback getting hit and was the key to remembering we disabled this in the pin muxing on the imx53 a year or so ago.

[TheAdmiral]

Followup note:

The perimx6.per file which was mentioned at the top of the post is not a Freescale file. This is a file developed by Lauterbach for use with their JTAG equipment. If you need this file, please contact Lauterbach directly. Freescale does not officially supply files from Lauterbach. Engineers within Freescale may not be using the latest files from Lauterbach and Freescale provides no official technical support directly to customer for Lauterbach files.

If Lauterbach cannot assist you with your questions, then Freescale can support Lauterbach to help answer your questions.

Just want to make sure that designers viewing this post get sent to the right source.

Cheers,

Mark