Dear All,

[alimuhammad]

I am using IMX6Q saberlite board and using linux-2.6.38 on it. I am having an issue in using its watchdog. The problem is this that it seems that there is no way to stop or disable watchdog  once  its activated. I have kept the nowayout parameter of driver(imx2_wdt) to 0. In the driver if a magic close is performed driver keeps on pinging watchdog in order to avoid a reboot. Now if a shutdown is performed the system restarts after 128 seconds. Is there any way to properly shutdown the system without a reboot due to watchdog.

Thanks,

Ali

[AnsonHuang]

Hi, Ali

     I looked into the wdog's driver, seems like there is no way to disble wdog once it is enabled, as its clock is always there(32K). On our i.MX6 SabreSD board, we have controlled the PMIC_ON_REQ signal to  shutdown external PMIC when a poweroff command is issued, then the wdog will be not able to reboot system, as the whole board are power off. However, the Sabrelite board did NOT have this pin used to control the power supply, as it did NOT have a PMIC on the board. So, my understanding is that the result you want may be negative. From the RM, wdog can be disabled if we set the bit 2 of its control register, but need system enter DEBUG mode, it is also not available.

[alimuhammad]

HI Huang,

               Thanks for replying. Do you have a guess what is power down counter feature in watchdog then. For example in Reference Manual it is mentioned that WDOG_B signal power downs the chip. I tried to trigger it in software but nothing happened.

Thanks,

Ali

[AnsonHuang]

Hi, Ali

     The WDOG_B pin we used is to reset external PMIC to do reset of whole board. You can refer to our patch commit number, but I think your case is power down case, you should use PMIC_ON_REQ pin to shut down PMIC, not reset. You can refer to our board file: arch/arm/mach-mx6/board-mx6q_sabresd.c's mx6_snvs_poweroff routine to enable this power off function. But you may need relative hardware rework on SabreLite board.

commit c9f6d63a6b91b4494d60191f9fa6cc3b1bd29847

Author: Robin Gong <b38343@freescale.com>

Date:   Mon Nov 19 10:04:46 2012 +0800

    ENGR00233366-4 WDOG LDO_BYPASS: fix wdog2 to reset external pmic in ldo bypass

    On Sabresd board design, the WDOG_B output to reset external pmic source from

    GPIO_2 pad which can be configured as WDOG2_WDOG_B, so if in ldo bypass mode,

    we should use WDOG2 reset signal to reset pmic, not WDOG1. Also, configure the

    related pins.

[EricNelson]

The PMIC_ON_REQ is not routed on the SABRE Lite, so that's not an option.

[EricNelson]

Note that if you have control over power through a GPIO, you can set the pm_power_off routine as shown here:

     https://github.com/boundarydevices/linux-imx6/blob/boundary-imx_3.0.35_4.1.0/arch/arm/mach-mx6/board...

[Yuri]

  You are right, "that there is no way to stop or disable watchdog once its activated";

according to the Reference Manual "WDE is a write one once only bit. Once software

performs a write "1" operation to this bit it cannot be reset/cleared until the next system

reset." But it is possible to suspend the watchdog timer during low power mode, using

WDZST bit of WDOGx_WCR register. Also, "there is an option of programmable interrupt

generation before the counter actually times out." Please look at Watchdog Interrupt Control

Register (WDOGx_WICR) description for more details.
   Nevertheless, it is possible to mask the reset in the System Reset Control register (SRC_SCR)

at address 0x20d8000.