Dealing with multiple PHYs on an MDIO bus

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Dealing with multiple PHYs on an MDIO bus

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adde_ado
Contributor III

Hi,

We are using a custom board based on i.MX8M-Plus. 

The board have two ethernet PHY:s Adin 1100 (10baseT1L) and Micrel KSZ9131 (1G).

The MDIO for Micrel is not connected, but Micrel PHY has its MDIO pins on the same MDIO bus, as ADIN 1100.

The Adin 1100 PHY  works fine but Micrel KSZ9131 have no link after Linux has booted. 

In Linux boot log we can see that correct driver is loaded and after that we are expecting message similar to link up/down, but that never comes up.

 

[    7.925149] Microchip KSZ9131 Gigabit PHY stmmac-1:03: attached PHY driver [Microchip KSZ9131 Gigabit PHY] (mii_bus:phy_addr=stmmac-1:03, irq=POLL)

 

 

We have configured device tree as follows but we are not sure if it is correct. We have seen similar examples with other CPU and with two fec but never with fec and eqos.  

 

 

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-mode = "rgmii-id";
	phy-handle = <&ksz9131>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;
            // No PHY here becouse ksz9131 PHY is connected to eqos MDIO bus.
	};
};

&eqos {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_eqos>;
	phy-mode = "rmii";
	phy-handle = <&adin1100>;
	status = "okay";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <0x1>;
		#size-cells = <0x0>;

		ksz9131: ethernet-phy@3 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0x3>;
		};

		adin1100: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0x0>;
		};
	};
};

pinctrl_eqos: eqosgrp {
	fsl,pins = <
	MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x3	/* MDIO */
	MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x3     /* MDC */
        MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK		0x4000001f /* RMII_REFCLK */
	MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x16				 
        MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x16 
	MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x16 /* RMII_TXEN */
	MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91 /* RMII_RXDV */
  	MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91 /* RMII_RXD0 */
	MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91 /* RMII_RXD1 */

	   >;
	};

  // This is either RGMII KSZ9131 for 1G eth phy
	pinctrl_fec: fecgrp {
		fsl,pins = <
			//MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
			//MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
      /*MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x19*/
		>;
	};

 

 

 

We have tested to read PHY registers with phytools on both PHY:s and that works fine.

Would appreciate any kind of help or suggestions.

 

  

 

 

 

 

 

 

 

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