Data gets written to all the address of memory

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Data gets written to all the address of memory

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niteshsahay
Contributor III

Hi

I am using MCIMX6U8DVM10AB dual lite processor and have interfaced MT29PZZZ8D5BKFTF-18 W.95L to the processor.

When i am writing any of the data to the any address of memory it is written to all the address lines.

What may be the possible reason for this.

Regards

Nitesh

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niteshsahay
Contributor III

Hi

Our concern is like data gets written to all the address line even though I am writing the data to only one particular address.

If there is a short or some manufacturing issue it will not write to all the address lines.

Also we are reading or writing through the JTAG.Is there some register settings we are missing out.

Regards

Nitesh

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igorpadykov
NXP TechSupport
NXP TechSupport

you can check your jtag register settings with

Sabre reference board, if read/write are ok, then problem

in your board only.

~igor

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niteshsahay
Contributor III

Hi Igor

Thanks for prompt reply.

I am attaching the JTAG register settings for your reference what we are using for our board.

Please let us know if something is missing out.

Part number used: MT29PZZZ8D5BKFTF-18 W.95L

Processor Used: MCIMX6U8DVM10AB

Regards

Nitesh

+91-9036032787

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igorpadykov
NXP TechSupport
NXP TechSupport

HI Nitesh

you can try jtag i.MX6DL scripts from package

https://community.freescale.com/servlet/JiveServlet/download/96412-13-277027/DDR_Stress_Tester_V1.0....

Best regards

igor

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niteshsahay
Contributor III

Hi Igor

The document attached is for DDR3.

But our application is LPDDR2.Please find our attachment that we have sent and please verify all the settings. We have tried all LPDDR2 settings available in Freescale site. It’s not working.

Can you please verify our LPDDR settings.

Regards

Nitesh

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igorpadykov
NXP TechSupport
NXP TechSupport

please check

i.MX6DL LPDDR2 Support for L3.0.35_4.0.0

Best regards

igor

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niteshsahay
Contributor III

Hi Igor

Thanks for the reply.

Could you please confirm that the pin DRAM_RESET pin must be pulled low or it can be NC also.

With Regards,

Nitesh Kumar

+91-9036032787

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igorpadykov
NXP TechSupport
NXP TechSupport

it can be NC as in i.MX6SL EVK schematic

Best regards

igor

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swapniltiwari
Contributor II

Hi igor,

i am not able to reset the lpddr2 through the script provided by freescale as nitesh is saying.

can you let me know how to read the mode register from lpddr2 so to make

sure whether communication from lpddr2 is happening or not or else

what is the command to verify through which i can assure that my lpddr2 is reacting to

the command triggered from trace32 or not.

regards

swapnil

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Nitesh

reason may be schematic or layout errors (broken, short circuit traces)

so actually one address is read/written. Recommended to read/write with jtag,

checking signals with oscilloscope.

Best regards

igor

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