Data bus connections between LPDDR4/X and iMX93.

[Bob_NXP_user]

Hi everyone,

I'm interfacing my iMX9332 with a LPDDR4X. I'm using the schematic document of MIMX93-EVK as a reference and I notice that some of the data pins [DQ8_A;DQ15_A] are not linked in an orderly manner.

As you can see from the image, DQ8_A of the LPDDR4 is linked to DQ11_A of iMX93, DQ9_a to DQ10_A and so on. Why was this solution chosen? 

I see that in this way the PCB tracks are way more ordered, I imagine that's the reason but I'm not sure at all. Can you help me? Can I route these pins as I prefer?

Regards,

Roberto

[JorgeCas · Accepted solution]

Hello,

As you mentioned the bits lanes could be swapped between the processor and the LPDDR4/X memories to ease routing.

Bit swapping within each slice/byte lane is OK. Byte swapping is NOT allowed.

Best regards.