DRAM register setting of i.MX7D

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DRAM register setting of i.MX7D

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ko-hey
Senior Contributor II

Hi all

My customer plan to use i.MX7D and LPDDR2 and have two questions about DRAM register setting.

About ZQ_RESISTOR_SHARED

 Would you teach me how to decide the value of ZQ_RESISTOR_SHARED register setting ?

 Is it depend on the type of DRAM memory ? 

 

 

About WR_ODT_HOLD

 

The description for WR_ODT_HOLD register is only for DDR3 in reference manual.

Which value should I set to the register when I use LPDDR2 ?

Can I leave it for the default settings?

Or do I need to set the value of tDQSS from the DRAM data sheet ?

 

If I need to set the value of tDQSS, there are min and max value of it in the DRAM datasheet so please teach me which value is correct.

 

 

 Ko-hey

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Yuri
NXP Employee
NXP Employee

Hello,

  Please look at my comments below.

 

1.

  For LPDDR2 that has, say, dual dies, which share a single ZQ resistor pin, corresponding
ZQ_RESISTOR_SHARED bit should be set to 1 for proper ZQ calibration.

 

2.

 Recommended value for LPDDR2 : (tDQSSmax / tCK) + 4

Have a great day,
Yuri

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