Hi
We are using two DDR3L in our design using i.MX6 Quad. Let me know we have to use DRAM_SDCLK_0 or DRAM_SDCLK_1 of i.MX6Q to interface two DDR3L Clocks
In Sabre brd, They are using DRAM_SDCLK_0 for Data32 to Data63 and DRAM_SDCLK_1 for Data0 to Data31, Please let me know why they follow this convention and what i have to follow since i am using two DDR3L only (DATA0-31)
Hi Sagar
both these clocks are identical so one can use them in any combination.
Best regards
igor
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