DMA support in Secure World for i.MX6

cancel
Showing results for 
Search instead for 
Did you mean: 

DMA support in Secure World for i.MX6

Jump to solution
626 Views
544151202
Contributor I

Hi, I'm using MCIMX6Q-SDB which equiped i.MX 6Quad* processor.

Now I can use SDMA to transmit data from non-secure memory to the peripheral‘s FIFO in Normal World. I want to use SDMA(Smart Direct Memory Access Controller) to transmit data between secure memory and secure peripheral in Secure World. But I don't find any guide about whether SDMA supports data transmission in this way.

When I tried to set the source memory address or/and destination device as secure, the DMA transfer transaction failed. Simply setting SDMA as secure peripheral using CSU could not help.

So I want to know: does i.MX6 supports DMA transmission between secure memory and secure peripheral in Secure World?

If yes, is there any guide about how to implement it?

If not, is there any alternative way to achieve the function I mentioned above?

0 Kudos
1 Solution
504 Views
igorpadykov
NXP TechSupport
NXP TechSupport

Hi

I am not aware of additional documentation for usage sdma in secure world,

in general one can check AIPS secure settings described in sect.13.4 Access Protections

Chapter 13 AHB to IP Bridge (AIPSTZ) i.MX 6Dual/6Quad Applications Processor Reference Manual

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

0 Kudos
2 Replies
505 Views
igorpadykov
NXP TechSupport
NXP TechSupport

Hi

I am not aware of additional documentation for usage sdma in secure world,

in general one can check AIPS secure settings described in sect.13.4 Access Protections

Chapter 13 AHB to IP Bridge (AIPSTZ) i.MX 6Dual/6Quad Applications Processor Reference Manual

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos
504 Views
544151202
Contributor I

Hi,Thanks for your quick reply.

I've read the Chapter 13 AHB to IP Bridge (AIPSTZ) carefully, and I printed the value of registers belonging to AIPSTZ, just before DMA transmission between secure memory and secure peripheral in Secure World.

The result is that:

1.for all masters:①they are trusted for write&read accesses ②accesses from them are not forced to user-mode ③write accesses from them are not bufferable by AIPSTZ.

2.for all Off-platform Peripheral:①they allow write accesses and don't need supervisor privilege level for accesses ②accesses from an untrusted master are allowed ③write accesses to them are not bufferable AIPSTZ.

Also, sect.13.4 Access Protections mention that “IP bus peripherals are subject to access control policies set in both CSU registers and AIPSTZ registers. An access is blocked if it is denied by either policy.” 

 

The information printed shows that the AIPSTZ is not the crux of the matter. Finally I solved it by setting the registers of CSU.

Thanks again.

Best regards.

0 Kudos