DMA interrupt on Major Loop complete without the XFER_DONE bit being set

[cashreuser]

Hello,

I am working with the EDMA on the MIMXRT1050-EVK prior to getting in our hardware.

I have created a couple of arrays and use memory2memory transfers to mimic what our hardware would send to us via the SPI ports. I have 2 files to mimic 2 devices and trigger a transfer using the PIT timer though the XBAR.

It seems that when the DMA requests occur within a microsecond of each other I will get an interrupt but the XFER_DONE in the CSR is not set. About every 1.1 seconds I get 3 interrupts without the XFER_DONE being set.

I have set one PIT to 10 us, and the other to 11 us...if I set them both to 10, I will not get any XFR_DONE bit set on the second channel, but every interrupt will occur.

Does anyone know why this would happen? I can't seem to find anything in documentation on this.

Regards,

Cash

[Carlos_Musich]

Hi Cash,

do you means it generate the DMA interrupt, but don't see the DONE flag in CSR register is set? could you share me the CSR register contents, also where to check CSR register? does it entry of DMA interrupt service routine?

is it function EDMA_HandleIRQ()? or others?

Regards,

Carlos

[cashreuser]

I found the problem.
I had 3 DMA in scatter gather mode going at the same time. I tried to do some processing in the interrupts, so the other TCDs would start executing. When I left the first interrupt, and the other interrupt fired, the DMA would show that the transfer was in progress.

I moved the processing outside the interrupt and all is good.

[Carlos_Musich]

Good to hear that Cash.

Thank you for sharing your solution.

Regards,

Carlos