DDR3 routing rules - different signal velocity on inner layers

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DDR3 routing rules - different signal velocity on inner layers

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jakob_u
Contributor I

The signal velocity on internal layers is over 10% slower than it is on outer layers ( http://www.altera.com/literature/an/an224.pdf figure 9). The difference is so big that if you ignore it, you may end up actually violating the allowed length differences (as stated in the HDG) by far.

Still, the fact that the signal propagates slower on the inner layers seems to never be mentioned in the IMX6 documentation.

What's going on here? Will the error just be absorbed by the safety factors?

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Yuri
NXP TechSupport
NXP TechSupport

  Generally it is highly recommended to provide careful PCB signals simulation to

analyze signal rise-times and trace lengths to see if we need to concern with

transmission line effects.  Corresponding simulation software includes most

significant factors. 

  The considerations of app notes / design checklists  are mainly just rules of

thumb in order to provide basis for estimations. In the same time, rules provided

there, are very difficult to satisfy, because they include some margin of safety.

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jakob_u
Contributor I

Dear Yuri! Based on your answer, we are trying to get the simulation started.

However, we cannot find an IBIS model for the IMX6Q. It seems to exist as it is mentioned here https://community.freescale.com/thread/310902 .

Could you provide a link to the IMX6Q IBIS model file?

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Yuri
NXP TechSupport
NXP TechSupport

The i.MX6 Q IBIS files should be updated soon and are not available on the Web now.

Would You please create a SR to get a preliminary version ?

(I think public community is not proper place to locate preliminary releases.) 

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