DDR3 memory calibration in a imx6d board

aicastell · ‎05-13-2016

Hi,

I'm trying to configure DDR3 RAM memory to start the calibration test in a i.MX6D board.

The problem is I don't see the output generated by the stress test in the debug console UART1. This is the first time I try to do this task, so probably I havent configured some register properly.

The memory connected in my custom board is a 1GB Micron with Part Number: MT41J256M16HA-125:E. According to datasheet, the micron memory has this configuration:

Configuration: 32 Meg x 16 x 8 banks

Refresh count: 8K

Row addressing: 32K

Bank addressing: 8

Column addressing: 1K

Page size: 2KB

CK: 1.25ns

CL: 11

Target RCD-RP-CL: 11-11-11

RCD (ns): 13.75

RP (ns): 13.75

CL (ns): 13.75

Data Rate (MT/s): 1600

RAS (MIN) Idd: 28

RC (MIN) Idd: 39

Hardware is designed with just one single Chip Select.

In order to setup control registers I am using I.MX6DQSDL DDR3 Script Aid V0.10.xlsx aid script with this values:

Device Information

===================================================

Manufacturer: Micron

Memory part number: MT41J256M16HA-125:E

Memory type: DDR3-800

DRAM density (Gb): 2

DRAM Bus Width: 16

Number of Banks: 8

Number of ROW Addresses: 15

Number of COLUMN Addresses: 10

Page Size (K): 2

Self-Refresh Temperature (SRT): Normal

CAS READ latency (CL) 11

tRCD=tRP=CL (ns) 13,75

tRC Min (ns) 39

tRAS Min (ns) 28

System Information

=================================================

i.Mx Part: i.Mx6D

Bus Width: 32

Density per chip select (Gb): 8

Number of Chip Selects used: 1

Total DRAM Density (Gb): 8

DRAM Clock Freq (Mhz): 400

DRAM Clock Cycle Time (ns): 2,5

Address Mirror (for CS1): Disable

SI Configuration

=================================================

DRAM DSE Setting - DQ/DQM (ohm): 48

DRAM DSE Setting - ADDR/CMD/CTL (ohm): 48

DRAM DSE Setting - CK (ohm): 48

DRAM DSE Setting - DQS (ohm): 48

System ODT Setting (ohm): 60

I am not sure if all these values are ok.

After translating generated RealView.inc to mwh/mww phys instructions, I can initialize DDR3 memory via netcat:

$ nc localhost 3333

> ddr_init

After initializing RAM with register values generated by the aid tool, I am able to read/write single RAM addresses:

> mww 0x10000000 0x1234567

mww 0x10000000 0x1234567

> mdw 0x10000000

0x10000000: 01234567

After that, I try to load the stress test tool 'ddr-test-uboot-jtag-mx6dq.elf' into internal RAM memory:

$ arm-none-eabi-gdb

> target remote localhost:3333

> load ddr_stress_tester_jtag_v2.52/ddr-test-uboot-jtag-mx6dq.elf

> cont

Process completes wthout any output error, but I don't see anything on the debug console (configured at 115200, 8N1).

I will appreciate any help on this.

Thank you in advance!

aicastell · ‎05-20-2016

Hello,

I have tried loading bin file as suggested, but I don't see any char written over UART1 console yet.

Attached are the steps I follow for your reference:

$ nc localhost 4444

> imx6d_init

imx6d_init

Call to imx6d_init...

number of cache level 1

imx6.cpu.0 cluster 0 core 0 multi core

target state: halted

target halted in Thumb state due to debug-request, current mode: Supervisor

cpsr: 0x600001f3 pc: 0x000024e4

MMU: disabled, D-Cache: disabled, I-Cache: disabled

Call to disable_wdog...

Call to imx6d_clock_init...

Call to imx6d_uart1_enable...

Call to imx6d_ddr3_1GB_init...

Ret from imx6d_init

> load_image ddr_stress_tester_v2.52/bin/ddr-test-mx6dq.bin 0x10000000

load_image ddr_stress_tester_v2.52/bin/ddr-test-mx6dq.bin 0x10000000

122016 bytes written at address 0x10000000

downloaded 122016 bytes in 76.891029s (1.550 KiB/s)

> step 0x10000000

step 0x10000000

target state: halted

target halted in Thumb state due to breakpoint, current mode: Supervisor

cpsr: 0x400001f3 pc: 0x10000002

MMU: disabled, D-Cache: disabled, I-Cache: disabled

> resume

resume

aicastell · ‎06-14-2016

Hello forum.

This issue is not fixed yet, I am still searching a solution for the described problem. It would be nice if some user with more experience on iMX.6 boards give some advice to try to discover what is wrong with this board.

Thank you in advance!

Best regards,

-- Ivan

engjoe · ‎08-26-2016

Also have this question, very similar set of steps but with the 6UL. No luck despite best efforts on UART register settings.

DDR stress test via USB doesn't always work, so that isn't a good answer Yuri.

ivancastell · ‎12-23-2016

We still haven't found any useful information to solve this issue... Completely stalled with this board...

Yuri · ‎07-21-2016

Hello,

Why do not use the DDR stress test, which is working via USB of i.MX6 ?

Regards,

Yuri.

Yuri · ‎05-16-2016

Hello,

Your (debug) configuration is not fully clear. The DDR stress test is intended to work in
bare metal environment.

i.MX6/7 DDR Stress Test Tool V2.52

Please use internal (USB) boot ROM loader of i.MX6 or JTAG debugger.

Have a great day,
Yuri

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aicastell · ‎05-16-2016

Hello Mr. Yuri.

I am loading the elf stress test binary you point in your link (ddr_stress_tester_jtag_v2.52/ddr-test-uboot-jtag-mx6dq.elf) using a SEGGER J-Link PLUS JTAG with openocd (version 0.9.0). So I translate RealView.inc generated by xlsx document to openocd instructions (mww and mwh).

I can provide any missing parameter you require to try to solve this issue.

Thank you for your answer.

Best regards,

-- Ivan

Yuri · ‎05-17-2016

Hello,

Can Your try to load and run memory image (.bin) file instead of .elf ?

Regards,

Yuri.

aicastell · ‎05-17-2016

Attached is the content of my openocd .cfg configuration file, so you can check all my control registers.

According to documentation, the DDR Stress Tester executable (starting with V2.20) has auto UART detection feature. Does this mean I don't have to setup any UART control register on my cfg file?.

Because after making different tests I don't see any output through the UART1, as a new test I tried adding a "imx6d_uart1_enable" procedure to my .cfg file in order to setup UART1 manually. But still I don't see any character on the console.

Any help on this will be really helpful.

Thank you in advance!

telnet_port 4444

gdb_port 3333

source [find interface/jlink.cfg]

source [find target/imx6.cfg]

adapter_khz 50

jtag_ntrst_delay 50

$_TARGETNAME configure -event reset-start { adapter_khz 50 }

$_TARGETNAME configure -event reset-assert "imx6d_init"

proc imx6d_init {} {

echo "Call to imx6d_init..."

halt

dap apcsw 1

imx6d_wdog_disable

imx6d_clock_init

imx6d_uart1_enable

imx6d_ddr3_1GB_init

echo "Ret from imx6d_init"

}

proc imx6d_wdog_disable {} {

echo "Call to disable_wdog..."

set WDOG1_WCR 0x020bc000

mwh phys $WDOG1_WCR 0x30

}

proc imx6d_clock_init {} {

echo "Call to imx6d_clock_init..."

set CCM_CCGR0 0x020c4068

set CCM_CCGR1 0x020c406c

set CCM_CCGR2 0x020c4070

set CCM_CCGR3 0x020c4074

set CCM_CCGR4 0x020c4078

set CCM_CCGR5 0x020c407c

set CCM_CCGR6 0x020c4080

set CCM_CCGR7 0x020c4084

# Enable all clocks

mww phys $CCM_CCGR0 0xffffffff

mww phys $CCM_CCGR1 0xffffffff

mww phys $CCM_CCGR2 0xffffffff

mww phys $CCM_CCGR3 0xffffffff

mww phys $CCM_CCGR4 0xffffffff

mww phys $CCM_CCGR5 0xffffffff

mww phys $CCM_CCGR6 0xffffffff

mww phys $CCM_CCGR7 0xffffffff

}

proc imx6d_uart1_enable {} {

echo "Call to imx6d_uart1_enable..."

set UART1_UCR1 0x02020080

set UART1_UCR2 0x02020084

set UART1_UCR3 0x02020088

set UART1_UCR4 0x0202008C

set UART1_URXD 0x02020000

set UART1_UTXD 0x02020040

set UART2_UCR1 0x021E8080

set UART2_UCR2 0x021E8084

set UART2_UCR3 0x021E8088

set UART2_UCR4 0x021E808C

set UART2_URXD 0x021E8000

set UART2_UTXD 0x021E8040

set UART3_UCR1 0x021EC080

set UART3_UCR2 0x021EC084

set UART3_UCR3 0x021EC088

set UART3_UCR4 0x021EC08C

set UART3_URXD 0x021EC000

set UART3_UTXD 0x021EC040

set UART4_UCR1 0x021F0080

set UART4_UCR2 0x021F0084

set UART4_UCR3 0x021F0088

set UART4_UCR4 0x021F008C

set UART4_URXD 0x021F0000

set UART4_UTXD 0x021F0040

# Enable UART1, data = 8bits

mww phys $UART1_UCR1 0x00000001

mww phys $UART1_UCR2 0x00000026

}

proc imx6d_ddr3_1GB_init {} {

echo "Call to imx6d_ddr3_1GB_init..."

set MX6_IOM_DRAM_DQM0 0x020e05ac

set MX6_IOM_DRAM_DQM1 0x020e05b4

set MX6_IOM_DRAM_DQM2 0x020e0528

set MX6_IOM_DRAM_DQM3 0x020e0520

set MX6_IOM_DRAM_DQM4 0x020e0514

set MX6_IOM_DRAM_DQM5 0x020e0510

set MX6_IOM_DRAM_DQM6 0x020e05bc

set MX6_IOM_DRAM_DQM7 0x020e05c4

set MX6_IOM_DRAM_CAS 0x020e056c

set MX6_IOM_DRAM_RAS 0x020e0578

set MX6_IOM_DRAM_RESET 0x020e057c

set MX6_IOM_DRAM_SDCLK_0 0x020e0588

set MX6_IOM_DRAM_SDCLK_1 0x020e0594

set MX6_IOM_DRAM_SDBA2 0x020e058c

set MX6_IOM_DRAM_SDCKE0 0x020e0590

set MX6_IOM_DRAM_SDCKE1 0x020e0598

set MX6_IOM_DRAM_SDODT0 0x020e059c

set MX6_IOM_DRAM_SDODT1 0x020e05a0

set MX6_IOM_DRAM_SDQS0 0x020e05a8

set MX6_IOM_DRAM_SDQS1 0x020e05b0

set MX6_IOM_DRAM_SDQS2 0x020e0524

set MX6_IOM_DRAM_SDQS3 0x020e051c

set MX6_IOM_DRAM_SDQS4 0x020e0518

set MX6_IOM_DRAM_SDQS5 0x020e050c

set MX6_IOM_DRAM_SDQS6 0x020e05b8

set MX6_IOM_DRAM_SDQS7 0x020e05c0

set MX6_IOM_GRP_B0DS 0x020e0784

set MX6_IOM_GRP_B1DS 0x020e0788

set MX6_IOM_GRP_B2DS 0x020e0794

set MX6_IOM_GRP_B3DS 0x020e079c

set MX6_IOM_GRP_B4DS 0x020e07a0

set MX6_IOM_GRP_B5DS 0x020e07a4

set MX6_IOM_GRP_B6DS 0x020e07a8

set MX6_IOM_GRP_B7DS 0x020e0748

set MX6_IOM_GRP_ADDDS 0x020e074c

set MX6_IOM_DDRMODE_CTL 0x020e0750

set MX6_IOM_GRP_DDRPKE 0x020e0758

set MX6_IOM_GRP_DDRMODE 0x020e0774

set MX6_IOM_GRP_CTLDS 0x020e078c

set MX6_IOM_GRP_DDR_TYPE 0x020e0798

set MX6_MMDC_P0_MDCTL 0x021b0000

set MX6_MMDC_P0_MDPDC 0x021b0004

set MX6_MMDC_P0_MDOTC 0x021b0008

set MX6_MMDC_P0_MDCFG0 0x021b000c

set MX6_MMDC_P0_MDCFG1 0x021b0010

set MX6_MMDC_P0_MDCFG2 0x021b0014

set MX6_MMDC_P0_MDMISC 0x021b0018

set MX6_MMDC_P0_MDSCR 0x021b001c

set MX6_MMDC_P0_MDREF 0x021b0020

set MX6_MMDC_P0_MDRWD 0x021b002c

set MX6_MMDC_P0_MDOR 0x021b0030

set MX6_MMDC_P0_MDASP 0x021b0040

set MX6_MMDC_P0_MAPSR 0x021b0404

set MX6_MMDC_P0_MPZQHWCTRL 0x021b0800

set MX6_MMDC_P0_MPWLDECTRL0 0x021b080c

set MX6_MMDC_P0_MPWLDECTRL1 0x021b0810

set MX6_MMDC_P0_MPODTCTRL 0x021b0818

set MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c

set MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820

set MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824

set MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828

set MX6_MMDC_P0_MPDGCTRL0 0x021b083c

set MX6_MMDC_P0_MPDGCTRL1 0x021b0840

set MX6_MMDC_P0_MPRDDLCTL 0x021b0848

set MX6_MMDC_P0_MPWRDLCTL 0x021b0850

set MX6_MMDC_P0_MPMUR0 0x021b08b8

set MX6_MMDC_P1_MDCTL 0x021b4000

set MX6_MMDC_P1_MDPDC 0x021b4004

set MX6_MMDC_P1_MDOTC 0x021b4008

set MX6_MMDC_P1_MDCFG0 0x021b400c

set MX6_MMDC_P1_MDCFG1 0x021b4010

set MX6_MMDC_P1_MDCFG2 0x021b4014

set MX6_MMDC_P1_MDMISC 0x021b4018

set MX6_MMDC_P1_MDSCR 0x021b401c

set MX6_MMDC_P1_MDREF 0x021b4020

set MX6_MMDC_P1_MDRWD 0x021b402c

set MX6_MMDC_P1_MDOR 0x021b4030

set MX6_MMDC_P1_MDASP 0x021b4040

set MX6_MMDC_P1_MAPSR 0x021b4404

set MX6_MMDC_P1_MPZQHWCTRL 0x021b4800

set MX6_MMDC_P1_MPWLDECTRL0 0x021b480c

set MX6_MMDC_P1_MPWLDECTRL1 0x021b4810

set MX6_MMDC_P1_MPODTCTRL 0x021b4818

set MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c

set MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820

set MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824

set MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828

set MX6_MMDC_P1_MPDGCTRL0 0x021b483c

set MX6_MMDC_P1_MPDGCTRL1 0x021b4840

set MX6_MMDC_P1_MPRDDLCTL 0x021b4848

set MX6_MMDC_P1_MPWRDLCTL 0x021b4850

set MX6_MMDC_P1_MPMUR0 0x021b48b8

#===========================================================================

# IOMUX

#===========================================================================

# DDR IO type

mww phys $MX6_IOM_GRP_DDR_TYPE 0x000C0000

mww phys $MX6_IOM_GRP_DDRPKE 0x00000000

# Clock

mww phys $MX6_IOM_DRAM_SDCLK_0 0x00000028

mww phys $MX6_IOM_DRAM_SDCLK_1 0x00000028

# Address

mww phys $MX6_IOM_DRAM_CAS 0x00000028

mww phys $MX6_IOM_DRAM_RAS 0x00000028

mww phys $MX6_IOM_GRP_ADDDS 0x00000028

# Control

mww phys $MX6_IOM_DRAM_RESET 0x00000028

mww phys $MX6_IOM_DRAM_SDBA2 0x00000000

mww phys $MX6_IOM_DRAM_SDODT0 0x00000028

mww phys $MX6_IOM_DRAM_SDODT1 0x00000028

mww phys $MX6_IOM_GRP_CTLDS 0x00000028

# Data Strobes

mww phys $MX6_IOM_DDRMODE_CTL 0x00020000

mww phys $MX6_IOM_DRAM_SDQS0 0x00000028

mww phys $MX6_IOM_DRAM_SDQS1 0x00000028

mww phys $MX6_IOM_DRAM_SDQS2 0x00000028

mww phys $MX6_IOM_DRAM_SDQS3 0x00000028

# mww phys $MX6_IOM_DRAM_SDQS4 0x00000028

# mww phys $MX6_IOM_DRAM_SDQS5 0x00000028

# mww phys $MX6_IOM_DRAM_SDQS6 0x00000028

# mww phys $MX6_IOM_DRAM_SDQS7 0x00000028

# Data

mww phys $MX6_IOM_GRP_DDRMODE 0x00020000

mww phys $MX6_IOM_GRP_B0DS 0x00000028

mww phys $MX6_IOM_GRP_B1DS 0x00000028

mww phys $MX6_IOM_GRP_B2DS 0x00000028

mww phys $MX6_IOM_GRP_B3DS 0x00000028

# mww phys $MX6_IOM_GRP_B4DS 0x00000028

# mww phys $MX6_IOM_GRP_B5DS 0x00000028

# mww phys $MX6_IOM_GRP_B6DS 0x00000028

# mww phys $MX6_IOM_GRP_B7DS 0x00000028

mww phys $MX6_IOM_DRAM_DQM0 0x00000028

mww phys $MX6_IOM_DRAM_DQM1 0x00000028

mww phys $MX6_IOM_DRAM_DQM2 0x00000028

mww phys $MX6_IOM_DRAM_DQM3 0x00000028

# mww phys $MX6_IOM_DRAM_DQM4 0x00000028

# mww phys $MX6_IOM_DRAM_DQM5 0x00000028

# mww phys $MX6_IOM_DRAM_DQM6 0x00000028

# mww phys $MX6_IOM_DRAM_DQM7 0x00000028

mww phys $MX6_MMDC_P0_MDSCR 0x00008000

#===========================================================================

# Calibration setup.

#===========================================================================

mww phys $MX6_MMDC_P0_MPZQHWCTRL 0xA1390003

# For target board, may need to run write leveling calibration to fine tune these settings.

mww phys $MX6_MMDC_P0_MPWLDECTRL0 0x00000000

mww phys $MX6_MMDC_P0_MPWLDECTRL1 0x00000000

## Read DQS Gating calibration

mww phys $MX6_MMDC_P0_MPDGCTRL0 0x00000000

mww phys $MX6_MMDC_P0_MPDGCTRL1 0x00000000

# Read calibration

mww phys $MX6_MMDC_P0_MPRDDLCTL 0x40404040

# Write calibration

mww phys $MX6_MMDC_P0_MPWRDLCTL 0x40404040

# Read data bit delay: (3 is the recommended default value, although out of reset value is 0)

mww phys $MX6_MMDC_P0_MPRDDQBY0DL 0x33333333

mww phys $MX6_MMDC_P0_MPRDDQBY1DL 0x33333333

mww phys $MX6_MMDC_P0_MPRDDQBY2DL 0x33333333

mww phys $MX6_MMDC_P0_MPRDDQBY3DL 0x33333333

# mww phys $MX6_MMDC_P1_MPRDDQBY0DL 0x33333333

# mww phys $MX6_MMDC_P1_MPRDDQBY1DL 0x33333333

# mww phys $MX6_MMDC_P1_MPRDDQBY2DL 0x33333333

# mww phys $MX6_MMDC_P1_MPRDDQBY3DL 0x33333333

# Complete calibration by forced measurement

mww phys $MX6_MMDC_P0_MPMUR0 0x00000800

# MMDC init

mww phys $MX6_MMDC_P0_MDPDC 0x0002002D

mww phys $MX6_MMDC_P0_MDOTC 0x00333040

mww phys $MX6_MMDC_P0_MDCFG0 0x2B2F5333

mww phys $MX6_MMDC_P0_MDCFG1 0xB5EB8B63

mww phys $MX6_MMDC_P0_MDCFG2 0x01FF00DB

mww phys $MX6_MMDC_P0_MDMISC 0x00011740

mww phys $MX6_MMDC_P0_MDSCR 0x00008000

mww phys $MX6_MMDC_P0_MDRWD 0x000026D2

mww phys $MX6_MMDC_P0_MDOR 0x002F1023

mww phys $MX6_MMDC_P0_MDASP 0x0000000F

mww phys $MX6_MMDC_P0_MDCTL 0x84190000

# Mode register writes

mww phys $MX6_MMDC_P0_MDSCR 0x02008032

mww phys $MX6_MMDC_P0_MDSCR 0x00008033

mww phys $MX6_MMDC_P0_MDSCR 0x00048031

mww phys $MX6_MMDC_P0_MDSCR 0x15208030

mww phys $MX6_MMDC_P0_MDSCR 0x04008040

mww phys $MX6_MMDC_P0_MDREF 0x00007800

mww phys $MX6_MMDC_P0_MPODTCTRL 0x00022227

mww phys $MX6_MMDC_P0_MDPDC 0x0002556D

mww phys $MX6_MMDC_P0_MAPSR 0x00011006

mww phys $MX6_MMDC_P0_MDSCR 0x00000000

}

DDR3 memory calibration in a imx6d board

DDR3 memory calibration in a imx6d board

i.MX6Dual