DDR3 clock connectivity on iMX6

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DDR3 clock connectivity on iMX6

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marksiggins
Contributor II

Hi all.

I've just noticed that on the iMX6 dev boards, both clocks for the DDR3 memories, are connected to the dram chips. i.e. sdclk0 and sdclk1 signals, even though in the 64-bit configurations used, all four rams are in CS0 space. Is this an error? If so, why does it still work? I would imagine that the calibration features rely on these connections being correct.

If, on our own board, a Solo design, so only 32-bit bus, with four 128Mx16 parts, I connect the clocks to the right rams, will it work?

i.e. two rams on CS0, one for d0-d15, the other for d16-d31. These driven by sdclk0 pair, sdcke0, etc.

The other two rams on CS1, one for d0-d15, the other for d16-d31. These driven by sdclk1 pair, sdcke1, etc.

This would make sense, right? So, why do the eval boards connect sdclk1 signals, to anything?

Many thanks,

Mark.

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woutersintecs
Contributor II

Yuri For a 64bit T-shape (4 memory devices) we use only CS0, is it possible to use only SDCLK0? The tight space prevents use to route both clocks.

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Yuri
NXP Employee
NXP Employee

Hello,

> we use only CS0, is it possible to use only SDCLK0?

yes,  why not ?

Regards,

Yuri.

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woutersintecs
Contributor II

That is exactly what I was wondering. Any idea why the combination of one CS0 with two CLKs was used in the reference design?

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Yuri
NXP Employee
NXP Employee

Hi,

since , practically, clock signals SDCLK0 and SDCLK1 are the same

it is possible to use any of them for PCB design.

Regards,

Yuri.

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Yuri
NXP Employee
NXP Employee

Signals CS0, ODT0, SDCKE0  relate to the CS0 channel.

Signals  CS1, ODT1, SDCKE1 relate to the CS1 channel.

Clock signals SDCLK0 and SDCLK1 are the same and do not

relate to CS0 or CS1 channels.

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marksiggins
Contributor II

Hi Yuri.

Thanks for the response! If that is true: OK, no problem. ... (Did I miss something in the documentation that tells me this?)

...but if you look in AN4467, (DDR Calibration for iMX6 Series), Sections 17 that describes Clock Delay Calibration, specifically mentions separate delays for SDCLK0 and SDCLK1.

So, either that document is in error, or, the clocks are not the same and it just happens that the calibration functions never program those fields to have different delays. I don't care which way it is, I just need to know.

The way the chip is pinned out, PCB routing of the clock pairs is certainly easier if I can keep them 'swapped'.

Cheers,

Mark.

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Yuri
NXP Employee
NXP Employee

Strictly speaking You are right regarding separate delays for SDCLK0 and SDCLK1.
In the same time, as we can see for reference design, in default state - for practical using

during PCB design - it is possible to consider both clocks as the same one.

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marksiggins
Contributor II

OK, so I can probably get away with keeping them swapped, if the pcb routing makes it difficult to have them 'logically' corrrect.

There is another oddity in the documentation: if you look in the reference manual for the Solo/DualLite, (I am designing with the Solo), Section 45.11.53 MMDC PHY CK Control Register (MMDCx_MPSDCTRL), the SDCLK1_DEL field is not there, there is only SDCLK0_DEL. It is the same for the Dual/Quad reference manual. However, for the SoloLite manual, both fields are there.

Is this just omissions from the Solo/DualLite, and Dual/Quad documents?

It would just be good to know, for certain, what is actually in the silicon.

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YixingKong
Senior Contributor IV

Mark

This discussion is closed since no activity. If you still need help, please feel free to reply with an update to this

discussion, or create another discussion.
Thanks,
Yixing

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YixingKong
Senior Contributor IV

Mark

Had your issue got resolved? If yes, we are going to close the discussion in 3 days. If you still need help please feel

free to contact Freescale.

Thanks,
Yixing

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