We designed our custom board which is using i.MX6Dual(MCIMX6D5EYM10AD) with only ONE DDR3(MT41K512M16HA)
Steps | Description |
1. 32bit read/write | I can write then read the data into any random address on DDR3 exactly |
2. Calibration | But when I calibrate with 528MHz, even 297MHz. It failed as the attached log |
3. Calibration | Then I changed the DSE value to 34/40/48 but it failed as the same log |
This is the log shows FAILED
Calibration will run at DDR frequency 528MHz. Type 'y' to continue.
If you want to run at other DDR frequency. Type 'n'
DDR Freq: 528 MHz
Would you like to run the write leveling calibration? (y/n)
Please enter the MR1 value on the initilization script
This will be re-programmed into MR1 after write leveling calibration
Enter as a 4-digit HEX value, example 0004, then hit enter
0004 You have entered: 0x0004
Start write leveling calibration
Write leveling calibration completed
MMDC_MPWLDECTRL0 ch0 after write level cal: 0x001F001F
MMDC_MPWLDECTRL1 ch0 after write level cal: 0x001F001F
Would you like to run the DQS gating, read/write delay calibration? (y/n)
Starting DQS gating calibration...
. . . . . . . . . . . . . . ERROR FOUND, we can't get suitable value !!!!
dram test fails for all values.
I have the same problem with the same DDR3 chip but the imx6 solo CPU. If pre-defined pattern is used, the hardware read DQS gating calibration return a hardware error, if predefined value is used, the hardware automatic calibration never stoped, that is, the HW_DG_EN bit is always 1 "1".
Hi Le
if all other tests passed, one can skip dqs gating calibration.
This may be caused by the hardware layout causing much noise between traces.
Background can be found on
p.22 Application Note AN4467 (Rev. 0, 10/2012) "i.MX 6 Series DDR Calibration"
http://www.freescale.com/files/32bit/doc/app_note/AN4467.pdf
"..as a proper DQS gating delay result. For i.MX 6 Series, however, the too-early
boundary detection was occasionally found to return wrong values (of 0 or 1 delay unit) using the hardware
calibration method. In these cases, the average value automatically placed in MMDC0/1_MPDGCTRLx
is thus also wrong. If using the hardware DQS Gating calibration sequence, it is the user’s responsibility
then to take the too-late boundary value, subtract a 3/4 cycle delay value, and write it to
MMDC0/1_MPDGCTRLx."
Best regards
igor
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Dear Igor,
In this case how can we booting Linux kernel or even Freescale SDK?
Hi Le
yes.
Best regards
igor