DDR3 Supply IMX6 Internal Power plane model

[preeteshrathod]

Can NXP Provide DDR3 Supply internal Power plane model which can be used in Signal integrity or Power Integrity Simulations?

[igorpadykov]

Hi Preetesh

as answered by app team :

Unfortunately we don't provide anything beyond what we currently have in the IBIS models.

Simulation model for i.MX6 power supply pins 

Best regards
igor
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[preeteshrathod]

So in that case Can I consider NVCC_DRAM supply pin R,L,C values provided in IBIS model as additional parameters of PDN network and no other die capacitance present internally on NVCC_DRAM? The reason for my curiosity is we have 64 bit bus DDR3 design. This design does not have any functional issues and is into production since long time. But one observation on the DDR3 interface which is surprising to me is that whenever any write burst starts we see ringing on DDR3 supply line (Decayed ringing probably you can see not more than 3 sinusoidal cycle with peak to peak amplitude of 150mV-180mV not more that) which is ok for us. But the surprising thing is that this noise voltage appears on all other DDR lines which are at logic 1 i.e. not switching during start of write burst (ADDR and CMD lines) with magnified voltage (ringing amplitude with peak to peak voltage of 300mV/350mV) and DDR Reset line shows biggest ringing amplitude (where it is almost 450mV-500mV) and I would like to estimate with PDN package RLC and Die PDN model (if available) if such noise can be estimated or at-least proved with some on paper or simulation analysis.